[Ask for help] i.MX6 dual display

Philipp Zabel p.zabel at pengutronix.de
Mon Dec 18 10:41:23 UTC 2017

Hi Sean,

On Mon, 2017-12-18 at 09:10 +0100, Sean Nyekjær wrote:
> Hi Philipp
> I have an i.MX6Q running 4.9 LTS with etnaviv.
> We would like to have both the HDMI and LVDS outputs enabled a once.
> If I enable hdmi and lvds in the devicetree, we have only output on the 
> hdmi port.

Probably both LVDS and HDMI are clocked from the video PLL (PLL5). It is
rather unlikely to have a combination of LVDS Display and HDMI mode that
can be driven from the same PLL frequency, as the LVDS serializer input
clock is 3.5 times or 7 times the LVDS pixel clock.
You can check the clock tree in /sys/kernel/debug/clk/clk_summary.

If you want to support connecting arbitrary monitors at all, you'll have
to move the LDB clock input to another PLL that can be set to the LVDS
serializer clock rate without disturbing other peripherals.
Due to a bug in the i.MX6Q LDB clock dividers, this has to be done once,
early during boot, using the assigned-clocks/assigned-clock-parents
device tree properties of the &clks node. To find example device trees,

  git grep -A3 assigned-clocks.*LDB_DI0_SEL arch/arm/boot/dts

> So basically I have 2 questions:
> Is it possible to have both LVDS and HDMI enabled at once from the same ipu?

Yes, if the resolution isn't too high. The IPU pixel clock / bandwidth
limitations depend on whether both DIs are active.
Also only one of the displays will have overlay plane support, if that
is relevant to you, since there's only one DP that can do composition in
each IPU.

> Can i move the HDMI output to the other ipu and how?

Yes, see arch/arm/boot/dts/imx6q-utilite-pro.dts for an example: After
severing the OF graph links between the IPU1 DIs and the HDMI encoder
in the device tree, the HDMI output can only be driven by IPU2:



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