[PATCH v2 0/8] Fix PSR-vblank-DMC interaction

Dhinakaran Pandiyan dhinakaran.pandiyan at intel.com
Tue Dec 19 05:26:51 UTC 2017

The first 3 patches are minor PSR improvements. The last 5 introduce a new
power domain to disable DC states when vblanks are required. The tricky
part is to enable and disable the DC_OFF power well in atomic context. I
have addressed the locking issues that CI caught in the last revision.

Dhinakaran Pandiyan (8):
  drm/i915/psr: Kill psr.source_ok flag.
  drm/i915/psr: CAN_PSR() macro to check for PSR source and sink
  drm/i915/psr: Avoid initializing PSR if there is no sink support.
  drm/vblank: Do not update vblank counts if vblanks are already
  drm/vblank: Restoring vblank counts after device runtime PM events.
  drm/i915: Use an atomic_t array to track power domain use count.
  drm/i915: Introduce a non-blocking power domain for vblank interrupts
  drm/i915: Use the vblank power domain disallow or disable DC states.

 drivers/gpu/drm/drm_vblank.c            |  56 ++++++---
 drivers/gpu/drm/i915/i915_debugfs.c     |  10 +-
 drivers/gpu/drm/i915/i915_drv.h         |  21 +++-
 drivers/gpu/drm/i915/i915_irq.c         |   6 +
 drivers/gpu/drm/i915/intel_drv.h        |   4 +
 drivers/gpu/drm/i915/intel_psr.c        |  30 +++--
 drivers/gpu/drm/i915/intel_runtime_pm.c | 195 ++++++++++++++++++++++++++++----
 include/drm/drm_vblank.h                |   1 +
 8 files changed, 268 insertions(+), 55 deletions(-)


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