[PATCH] drm: mxsfb: Assure CTRL and CTRL1 values are latched into HW

Marek Vasut marex at denx.de
Sun Feb 26 15:52:05 UTC 2017


For reasons unknown, the first write into CTRL and CTRL1 registers
is not actually latched into the hardware and the data read back
are the reset values. Second write into the same registers has the
expected effect though and a readback returns the written values.
Add the second write.

Signed-off-by: Marek Vasut <marex at denx.de>
Cc: Breno Lima <breno.lima at nxp.com>
Cc: Daniel Vetter <daniel.vetter at ffwll.ch>
Cc: Dave Airlie <airlied at redhat.com>
Cc: Fabio Estevam <fabio.estevam at nxp.com>
Cc: Stefan Agner <stefan at agner.ch>
---
 drivers/gpu/drm/mxsfb/mxsfb_crtc.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/mxsfb/mxsfb_crtc.c b/drivers/gpu/drm/mxsfb/mxsfb_crtc.c
index 6d701d2c362d..f02d23d55995 100644
--- a/drivers/gpu/drm/mxsfb/mxsfb_crtc.c
+++ b/drivers/gpu/drm/mxsfb/mxsfb_crtc.c
@@ -84,6 +84,8 @@ static int mxsfb_set_pixel_fmt(struct mxsfb_drm_private *mxsfb)
 
 	writel(ctrl1, mxsfb->base + LCDC_CTRL1);
 	writel(ctrl, mxsfb->base + LCDC_CTRL);
+	writel(ctrl1, mxsfb->base + LCDC_CTRL1);
+	writel(ctrl, mxsfb->base + LCDC_CTRL);
 
 	return 0;
 }
-- 
2.11.0



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