[PATCH 2/4] gpu: ipu-v3: add unsynchronised DP channel disabling

Philipp Zabel p.zabel at pengutronix.de
Mon Feb 27 11:44:27 UTC 2017


On Mon, 2017-02-27 at 12:33 +0100, Lucas Stach wrote:
> Am Montag, den 27.02.2017, 12:28 +0100 schrieb Philipp Zabel:
> > When disabling the foreground DP channel during a modeset, the DC is
> > already disabled without waiting for end of frame. There is no reason
> > to wait for a frame boundary before updating the DP registers in that
> > case.
> > Add support to apply updates immediately. No functional changes, yet.
> > 
> > Signed-off-by: Philipp Zabel <p.zabel at pengutronix.de>
> > ---
> >  drivers/gpu/drm/imx/ipuv3-plane.c |  2 +-
> >  drivers/gpu/ipu-v3/ipu-common.c   |  8 +++++---
> >  drivers/gpu/ipu-v3/ipu-dp.c       | 12 ++++++------
> >  drivers/gpu/ipu-v3/ipu-prv.h      |  7 ++++++-
> >  include/video/imx-ipu-v3.h        |  2 +-
> >  5 files changed, 19 insertions(+), 12 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/imx/ipuv3-plane.c b/drivers/gpu/drm/imx/ipuv3-plane.c
> > index 24819c9c36400..55991d46ced50 100644
> > --- a/drivers/gpu/drm/imx/ipuv3-plane.c
> > +++ b/drivers/gpu/drm/imx/ipuv3-plane.c
> > @@ -181,7 +181,7 @@ static int ipu_disable_plane(struct drm_plane *plane)
> >  	ipu_idmac_wait_busy(ipu_plane->ipu_ch, 50);
> >  
> >  	if (ipu_plane->dp)
> > -		ipu_dp_disable_channel(ipu_plane->dp);
> > +		ipu_dp_disable_channel(ipu_plane->dp, true);
> >  	ipu_idmac_disable_channel(ipu_plane->ipu_ch);
> >  	ipu_dmfc_disable_channel(ipu_plane->dmfc);
> >  	if (ipu_plane->dp)
> > diff --git a/drivers/gpu/ipu-v3/ipu-common.c b/drivers/gpu/ipu-v3/ipu-common.c
> > index 8368e6f766ee5..86b87d620150c 100644
> > --- a/drivers/gpu/ipu-v3/ipu-common.c
> > +++ b/drivers/gpu/ipu-v3/ipu-common.c
> > @@ -51,15 +51,17 @@ int ipu_get_num(struct ipu_soc *ipu)
> >  }
> >  EXPORT_SYMBOL_GPL(ipu_get_num);
> >  
> > -void ipu_srm_dp_sync_update(struct ipu_soc *ipu)
> > +void ipu_srm_dp_update(struct ipu_soc *ipu, bool sync)
> >  {
> >  	u32 val;
> >  
> >  	val = ipu_cm_read(ipu, IPU_SRM_PRI2);
> > -	val |= 0x8;
> > +	val &= DP_S_SRM_MODE_MASK;
> 
> Should probably be ~DP_S_SRM_MODE_MASK.

Indeed, thanks for catching this.

This had no effect since the IPU auto-clears the DP_S_SRM_MODE field,
and all other non-zero fields in this register are only SRM update
priorities for modules that don't use the SRM for register updates.

regards
Philipp



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