[PATCH 4/9] gpu: ipu-v3: add DT binding for the Prefetch Resolve Gasket

[Rob Herring]

On Fri, Feb 17, 2017 at 07:28:25PM +0100, Lucas Stach wrote:
> This adds the the devicetree binding for the Prefetch Resolve Gasket,
> as found on i.MX6 QuadPlus.
> The PRG is fairly simple in that it only has a configuration register
> range and two clocks, one for the AHB slave port and one for the AXI
> ports and the functional units.
> 
> The PRE connections need to be described in the DT, as the PRE<->PRG
> assignment is a mix between fixed and muxable connections.
> 
> Signed-off-by: Lucas Stach <l.stach at pengutronix.de>
> ---
>  .../bindings/display/imx/fsl-imx-drm.txt           | 25 ++++++++++++++++++++++
>  1 file changed, 25 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt b/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt
> index 1bd777d7c37d..5e4b8b13b9f8 100644
> --- a/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt
> +++ b/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt
> @@ -79,6 +79,31 @@ pre at 021c8000 {
>  	fsl,ocram = <&ocram2>;
>  };
>  
> +Freescale i.MX PRG (Prefetch Resolve Gasket)
> +============================================
> +
> +Required properties:
> +- compatible: should be "fsl,imx6qp-prg"
> +- reg: should be register base and length as documented in the
> +  datasheet
> +- clocks : phandles to the PRG ipg and axi clock inputs, as described
> +  in Documentation/devicetree/bindings/clock/clock-bindings.txt and
> +  Documentation/devicetree/bindings/clock/imx6q-clock.txt.
> +- clock-names: should be "ipg" and "axi"
> +- fsl,pres: phandles to the PRE units attached to this PRG, with the fixed
> +  PRE as the first entry and the muxable PREs following.
> +
> +example:
> +
> +prg at 021cc000 {

Drop the leading 0. With that,

Acked-by: Rob Herring <robh at kernel.org>

> +	compatible = "fsl,imx6qp-prg";
> +	reg = <0x021cc000 0x1000>;
> +	clocks = <&clks IMX6QDL_CLK_PRG0_APB>,
> +		 <&clks IMX6QDL_CLK_PRG0_AXI>;
> +	clock-names = "ipg", "axi";
> +	fsl,pres = <&pre1>, <&pre2>, <&pre3>;
> +};
> +
>  Parallel display support
>  ========================
>  
> -- 
> 2.11.0
> 
> --
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