[PATCH v5 1/2] drm_fourcc: Add new P010, P016 video format

[Ville Syrjälä]

On Tue, Feb 28, 2017 at 08:08:55AM -0800, Clint Taylor wrote:
> On 02/28/2017 03:56 AM, Ville Syrjälä wrote:
> > On Mon, Feb 27, 2017 at 02:57:58PM -0800, clinton.a.taylor at intel.com wrote:
> >> From: Clint Taylor <clinton.a.taylor at intel.com>
> >>
> >> P010 is a planar 4:2:0 YUV with interleaved UV plane, 10 bits per
> >> channel video format. Rockchip's vop support this video format(little
> >> endian only) as the input video format.
> >>
> >> P016 is a planar 4:2:0 YUV 12 bits per channel
> >>
> >> P016 is a planar 4:2:0 YUV with interleaved UV plane, 16 bits per
> >> channel video format.
> >>
> >> V3: Added P012 and fixed cpp for P010
> >> V4: format definition refined per review
> >> V5: Format comment block for each new pixel format
> >>
> >> Cc: Daniel Stone <daniel at fooishbar.org>
> >> Cc: Ville Syrjälä <ville.syrjala at linux.intel.com>
> >>
> >> Signed-off-by: Randy Li <ayaka at soulik.info>
> >> Signed-off-by: Clint Taylor <clinton.a.taylor at intel.com>
> >> ---
> >>  drivers/gpu/drm/drm_fourcc.c  |    4 ++++
> >>  include/uapi/drm/drm_fourcc.h |   21 +++++++++++++++++++++
> >>  2 files changed, 25 insertions(+)
> >>
> >> diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
> >> index 90d2cc8..5494764 100644
> >> --- a/drivers/gpu/drm/drm_fourcc.c
> >> +++ b/drivers/gpu/drm/drm_fourcc.c
> >> @@ -165,6 +165,10 @@ const struct drm_format_info *__drm_format_info(u32 format)
> >>  		{ .format = DRM_FORMAT_UYVY,		.depth = 0,  .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1 },
> >>  		{ .format = DRM_FORMAT_VYUY,		.depth = 0,  .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1 },
> >>  		{ .format = DRM_FORMAT_AYUV,		.depth = 0,  .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1 },
> >> +		/* FIXME a pixel in Y for P010 is 10 bits */
> >> +		{ .format = DRM_FORMAT_P010,		.depth = 0,  .num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2 },
> >> +		{ .format = DRM_FORMAT_P012,		.depth = 0,  .num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2 },
> >> +		{ .format = DRM_FORMAT_P016,		.depth = 0,  .num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2 },
> >>  	};
> >>
> >>  	unsigned int i;
> >> diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> >> index ef20abb..306f979 100644
> >> --- a/include/uapi/drm/drm_fourcc.h
> >> +++ b/include/uapi/drm/drm_fourcc.h
> >> @@ -128,6 +128,27 @@
> >>  #define DRM_FORMAT_NV42		fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
> >>
> >>  /*
> >> + * 2 plane YCbCr MSB aligned
> >> + * index 0 = Y plane, [15:0] Y:x [10:6] little endian
> >> + * index 1 = Cb:Cr plane, [31:0] Cb:x:Cr:x [10:6:10:6] little endian
> >> + */
> >
> > Your Cb and Cr look swapped (unless my memory is playing tricks on me).
> 
> This is the information I have:
>                           Y     U    V
> YUV 4:2:0  8 bpc - NV12  7:0  15:8  7:0
> YUV 4:2:0 10 bpc - P010 15:6  31:22 15:6
> YUV 4:2:0 12 bpc - P012 15:4  31:20 15:4
> YUV 4:2:0 16 bpc - P016 15:0  31:16 15:0

I don't think those match the MS docs

https://msdn.microsoft.com/en-us/library/windows/desktop/bb970578%28v=vs.85%29.aspx

> 
> -clint
> 
> >
> >> +#define DRM_FORMAT_P010		fourcc_code('P', '0', '1', '0') /* 2x2 subsampled Cb:Cr plane 10 bits per channel */
> >> +
> >> +/*
> >> + * 2 plane YCbCr MSB aligned
> >> + * index 0 = Y plane, [15:0] Y:x [12:4] little endian
> >> + * index 1 = Cb:Cr plane, [31:0] Cb:x:Cr:x [12:4:12:4] little endian
> >> + */
> >> +#define DRM_FORMAT_P012		fourcc_code('P', '0', '1', '2') /* 2x2 subsampled Cb:Cr plane 12 bits per channel */
> >> +
> >> +/*
> >> + * 2 plane YCbCr MSB aligned
> >> + * index 0 = Y plane, [15:0] Y little endian
> >> + * index 1 = Cb:Cr plane, [31:0] Cb:Cr [16:16] little endian
> >> + */
> >> +#define DRM_FORMAT_P016		fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cb:Cr plane 16 bits per channel */
> >> +
> >> +/*
> >>   * 3 plane YCbCr
> >>   * index 0: Y plane, [7:0] Y
> >>   * index 1: Cb plane, [7:0] Cb
> >> --
> >> 1.7.9.5
> >

-- 
Ville Syrjälä
Intel OTC