[PATCH 1/3] drm: bridge: dw-hdmi: Define and use macros for PHY register addresses

Thu Jan 12 01:45:31 UTC 2017

Hi Laurent,

在 2017年01月12日 07:49, Laurent Pinchart 写道:
> Replace the hardcoded register address numerical values with macros to
> clarify the code.
>
> This change has been tested by comparing the assembly code before and
> after the change.
>
> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas at ideasonboard.com>
> ---
>   drivers/gpu/drm/bridge/dw-hdmi.c | 35 ++++++++++++---------
>   drivers/gpu/drm/bridge/dw-hdmi.h | 66 ++++++++++++++++++++++++++++++++++++++++
>   2 files changed, 86 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/bridge/dw-hdmi.c b/drivers/gpu/drm/bridge/dw-hdmi.c
> index ef4f2f96ed2c..6e605fd910ef 100644
> --- a/drivers/gpu/drm/bridge/dw-hdmi.c
> +++ b/drivers/gpu/drm/bridge/dw-hdmi.c
> @@ -997,21 +997,26 @@ static int hdmi_phy_configure(struct dw_hdmi *hdmi, int cscon)
>   		    HDMI_PHY_I2CM_SLAVE_ADDR);
>   	hdmi_phy_test_clear(hdmi, 0);
>   
> -	hdmi_phy_i2c_write(hdmi, mpll_config->res[0].cpce, 0x06);
> -	hdmi_phy_i2c_write(hdmi, mpll_config->res[0].gmp, 0x15);
> -
> -	/* CURRCTRL */
> -	hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[0], 0x10);
> -
> -	hdmi_phy_i2c_write(hdmi, 0x0000, 0x13);  /* PLLPHBYCTRL */
> -	hdmi_phy_i2c_write(hdmi, 0x0006, 0x17);
> -
> -	hdmi_phy_i2c_write(hdmi, phy_config->term, 0x19);  /* TXTERM */
> -	hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr, 0x09); /* CKSYMTXCTRL */
> -	hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr, 0x0E); /* VLEVCTRL */
> -
> -	/* REMOVE CLK TERM */
> -	hdmi_phy_i2c_write(hdmi, 0x8000, 0x05);  /* CKCALCTRL */
> +	hdmi_phy_i2c_write(hdmi, mpll_config->res[0].cpce,
> +			   HDMI_3D_TX_PHY_CPCE_CTRL);
> +	hdmi_phy_i2c_write(hdmi, mpll_config->res[0].gmp,
> +			   HDMI_3D_TX_PHY_GMPCTRL);
> +	hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[0],
> +			   HDMI_3D_TX_PHY_CURRCTRL);
> +
> +	hdmi_phy_i2c_write(hdmi, 0, HDMI_3D_TX_PHY_PLLPHBYCTRL);
> +	hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_FB_CLK,
> +			   HDMI_3D_TX_PHY_MSM_CTRL);
> +
> +	hdmi_phy_i2c_write(hdmi, phy_config->term, HDMI_3D_TX_PHY_TXTERM);
> +	hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr,
> +			   HDMI_3D_TX_PHY_CKSYMTXCTRL);
> +	hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr,
> +			   HDMI_3D_TX_PHY_VLEVCTRL);
> +
> +	/* Override and disable clock termination. */
> +	hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_CKCALCTRL_OVERRIDE,
> +			   HDMI_3D_TX_PHY_CKCALCTRL);
>   
>   	dw_hdmi_phy_enable_powerdown(hdmi, false);
>   
> diff --git a/drivers/gpu/drm/bridge/dw-hdmi.h b/drivers/gpu/drm/bridge/dw-hdmi.h
> index a4fd64a203c9..f3c149c88d71 100644
> --- a/drivers/gpu/drm/bridge/dw-hdmi.h
> +++ b/drivers/gpu/drm/bridge/dw-hdmi.h
> @@ -1085,4 +1085,70 @@ enum {
>   	HDMI_I2CM_CTLINT_ARB_MASK = 0x4,
>   };
>   
> +/*
> + * HDMI 3D TX PHY registers
> + */

Why is there 3D related words？I did not find "3D" words in PHY IP vendor 
document.
> +#define HDMI_3D_TX_PHY_PWRCTRL			0x00
> +#define HDMI_3D_TX_PHY_SERDIVCTRL		0x01
> +#define HDMI_3D_TX_PHY_SERCKCTRL		0x02
> +#define HDMI_3D_TX_PHY_SERCKKILLCTRL		0x03
> +#define HDMI_3D_TX_PHY_TXRESCTRL		0x04
> +#define HDMI_3D_TX_PHY_CKCALCTRL		0x05
> +#define HDMI_3D_TX_PHY_CPCE_CTRL		0x06
> +#define HDMI_3D_TX_PHY_TXCLKMEASCTRL		0x07
> +#define HDMI_3D_TX_PHY_TXMEASCTRL		0x08
> +#define HDMI_3D_TX_PHY_CKSYMTXCTRL		0x09
> +#define HDMI_3D_TX_PHY_CMPSEQCTRL		0x0a
> +#define HDMI_3D_TX_PHY_CMPPWRCTRL		0x0b
> +#define HDMI_3D_TX_PHY_CMPMODECTRL		0x0c
> +#define HDMI_3D_TX_PHY_MEASCTRL			0x0d
> +#define HDMI_3D_TX_PHY_VLEVCTRL			0x0e
> +#define HDMI_3D_TX_PHY_D2ACTRL			0x0f
> +#define HDMI_3D_TX_PHY_CURRCTRL			0x10
> +#define HDMI_3D_TX_PHY_DRVANACTRL		0x11
> +#define HDMI_3D_TX_PHY_PLLMEASCTRL		0x12
> +#define HDMI_3D_TX_PHY_PLLPHBYCTRL		0x13
> +#define HDMI_3D_TX_PHY_GRP_CTRL			0x14
> +#define HDMI_3D_TX_PHY_GMPCTRL			0x15
> +#define HDMI_3D_TX_PHY_MPLLMEASCTRL		0x16
> +#define HDMI_3D_TX_PHY_MSM_CTRL			0x17
> +#define HDMI_3D_TX_PHY_SCRPB_STATUS		0x18
> +#define HDMI_3D_TX_PHY_TXTERM			0x19
> +#define HDMI_3D_TX_PHY_PTRPT_ENBL		0x1a
> +#define HDMI_3D_TX_PHY_PATTERNGEN		0x1b
> +#define HDMI_3D_TX_PHY_SDCAP_MODE		0x1c
> +#define HDMI_3D_TX_PHY_SCOPEMODE		0x1d
> +#define HDMI_3D_TX_PHY_DIGTXMODE		0x1e
> +#define HDMI_3D_TX_PHY_STR_STATUS		0x1f
> +#define HDMI_3D_TX_PHY_SCOPECNT0		0x20
> +#define HDMI_3D_TX_PHY_SCOPECNT1		0x21
> +#define HDMI_3D_TX_PHY_SCOPECNT2		0x22
> +#define HDMI_3D_TX_PHY_SCOPECNTCLK		0x23
> +#define HDMI_3D_TX_PHY_SCOPESAMPLE		0x24
> +#define HDMI_3D_TX_PHY_SCOPECNTMSB01		0x25
> +#define HDMI_3D_TX_PHY_SCOPECNTMSB2CK		0x26
> +
> +/* HDMI_3D_TX_PHY_CKCALCTRL values */
> +#define HDMI_3D_TX_PHY_CKCALCTRL_OVERRIDE		BIT(15)
> +
> +/* HDMI_3D_TX_PHY_MSM_CTRL values */
> +#define HDMI_3D_TX_PHY_MSM_CTRL_MPLL_PH_SEL_CK		BIT(13)
> +#define HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_CLK_REF_MPLL	(0 << 1)
> +#define HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_OFF		(1 << 1)
> +#define HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_PCLK		(2 << 1)
> +#define HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_FB_CLK		(3 << 1)
> +#define HDMI_3D_TX_PHY_MSM_CTRL_SCOPE_CK_SEL		BIT(0)
> +
> +/* HDMI_3D_TX_PHY_PTRPT_ENBL values */
> +#define HDMI_3D_TX_PHY_PTRPT_ENBL_OVERRIDE		BIT(15)
> +#define HDMI_3D_TX_PHY_PTRPT_ENBL_PG_SKIP_BIT2		BIT(8)
> +#define HDMI_3D_TX_PHY_PTRPT_ENBL_PG_SKIP_BIT1		BIT(7)
> +#define HDMI_3D_TX_PHY_PTRPT_ENBL_PG_SKIP_BIT0		BIT(6)
> +#define HDMI_3D_TX_PHY_PTRPT_ENBL_CK_REF_ENB		BIT(5)
> +#define HDMI_3D_TX_PHY_PTRPT_ENBL_RCAL_ENB		BIT(4)
> +#define HDMI_3D_TX_PHY_PTRPT_ENBL_TX_CLK_ALIGN_ENB	BIT(3)
> +#define HDMI_3D_TX_PHY_PTRPT_ENBL_TX_READY		BIT(2)
> +#define HDMI_3D_TX_PHY_PTRPT_ENBL_CKO_WORD_ENB		BIT(1)
> +#define HDMI_3D_TX_PHY_PTRPT_ENBL_REFCLK_ENB		BIT(0)
> +
>   #endif /* __DW_HDMI_H__ */

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