[PATCH 1/3] drm: bridge: dw-hdmi: Define and use macros for PHY register addresses
Nickey.Yang
nickey.yang at rock-chips.com
Mon Jan 16 01:44:44 UTC 2017
Hi Laurent,
在 2017年01月13日 21:46, Laurent Pinchart 写道:
> On Friday 13 Jan 2017 09:32:54 Nickey.Yang wrote:
>> 在 2017年01月12日 23:26, Laurent Pinchart 写道:
>>> On Thursday 12 Jan 2017 09:45:31 Nickey.Yang wrote:
>>>> 在 2017年01月12日 07:49, Laurent Pinchart 写道:
>>>>> Replace the hardcoded register address numerical values with macros to
>>>>> clarify the code.
>>>>>
>>>>> This change has been tested by comparing the assembly code before and
>>>>> after the change.
>>>>>
>>>>> Signed-off-by: Laurent Pinchart
>>>>> <laurent.pinchart+renesas at ideasonboard.com>
>>>>> ---
>>>>>
>>>>> drivers/gpu/drm/bridge/dw-hdmi.c | 35 ++++++++++++---------
>>>>> drivers/gpu/drm/bridge/dw-hdmi.h | 66 +++++++++++++++++++++++++++++++++
>>>>> 2 files changed, 86 insertions(+), 15 deletions(-)
>>>>>
>>>>>
>>>>> diff --git a/drivers/gpu/drm/bridge/dw-hdmi.h
>>>>> b/drivers/gpu/drm/bridge/dw-hdmi.h index a4fd64a203c9..f3c149c88d71
>>>>> 100644
>>>>> --- a/drivers/gpu/drm/bridge/dw-hdmi.h
>>>>> +++ b/drivers/gpu/drm/bridge/dw-hdmi.h
>>>>> @@ -1085,4 +1085,70 @@ enum {
>>>>>
>>>>> HDMI_I2CM_CTLINT_ARB_MASK = 0x4,
>>>>>
>>>>> };
>>>>>
>>>>> +/*
>>>>> + * HDMI 3D TX PHY registers
>>>>> + */
>>>> Why is there 3D related words？
>>> The register names come from the i.MX6 datasheet. I don't have access to
>>> any PHY datasheet from Synopsys, and the Rockchip RK3288 manuals I've
>>> been able to find don't document the HDMI PHY register. As the PHY used
>>> by i.MX6 is a "DWC HDMI 3D TX PHY", I'd used that name in the code.
>>>
>>> The "DWC MHL PHY" used by RK3288 seems to be use a similar (if not
>>> identical) registers map, at least for the registers configured by the
>>> driver. The "DWC HDMI 2.0 TX PHY" PHY used by R-Car Gen3, however, seems
>>> not to have a compatible register interface, except for the
>>> HDMI_3D_TX_PHY_PTRPT_ENBL register.
>>>
>>> I'm open to suggestions for a better naming scheme. If you have additional
>>> information that I don't have access to, please feel free to use them to
>>> propose improvements or to point out my mistakes :-)
>>>
>>>> I did not find "3D" words in PHY IP vendor document.
>>> How is the PHY named in the documentation you have access to ?
>> just remove 3D word，such as name HDMI_TX_PHY_PWRCTRL instead of
>> HDMI_3D_TX_PHY_PWRCTRL
>> in doc: HDMI Tx PHY for GLOBAL FOUNDRIES 28-nm SLP/1.8 V Databook,
>> LCA Edition
>> 11.1 Control Registers Module Design Architecture
> https://www.synopsys.com/dw/ipdir.php?ds=dwc_hdmi_14_csds_tx doesn't list that
> document, but mentions "DesignWare Cores HDMI 3D TX PHY for GLOBALFOUNDARIES
> 28-nm SLP/1.8 V Databook". The description of the corresponding PHY, however,
> is "HDMI 1.4 TX PHY 3.4Gbps in GF 28nm SLP 1.8V, East/West Poly Orientation".
>
> I assume that HDMI 1.4 TX PHYs originally didn't have 3D support, and new PHYs
> with 3D support were then named "HDMI 3D TX PHY". After some time PHYs without
> 3D support were dropped from the product line, and 3D then got dropped from
> the name.
I agree with your point, I have compared the whole of registers, most of
them is the same.
This patch should not affect use, so i think weather the 3D words are
reserved or not is OK.
> We could use the "HDMI_14_TX_PHY" prefix, to differentiate the registers from
> the HDMI 2.0 TX PHY registers that would use a "HDMI_20_TX_PHY" prefix.
> "HDMI_TX_PHY" prefix could be used for registers common between the two PHY
> types. I'm sure that wouldn't cover the whole product range, but with no
> additional information it's hard to come up with a better proposal (actually
> even this wouldn't be very easy, as I don't have much documentation about the
> HDMI 2.0 TX PHY registers).
>
> By the way, does your HDMI TX controller databook (not the TX PHY but the TX
> controller) mention "HDMI 3D TX PHY" in the config2_id register (0x0006)
> documentation ? How does it name PHY type 0xF2 for instance ? And PHY type
> 0xC2, which I believe is the PHY used by the RK3288 (please correct me if I'm
> wrong there) ?
Configuration Identification Register 2(0x0006)
Bits Name Description
7:0 phytype Indicates the type of PHY interface
selected:
0x00: Legacy PHY (HDMI TX PHY)
0xB2: PHY_HDMI-MHL with HEAC
0xC2: PHY_HDMI-MHL
0xF2: PHY_GEN2 (HDMI 3D TX PHY)
0xE2: PHY_GEN2 (HDMI 3D TX
PHY) + HEAC PHY
and in rk3288
root at linaro-alip:~# io -4 0xff980018
ff980018: 000000c2
RK3288 use "PHY_HDMI-MHL"
>>>>> +#define HDMI_3D_TX_PHY_PWRCTRL 0x00
>>>>> +#define HDMI_3D_TX_PHY_SERDIVCTRL 0x01
>>>>> +#define HDMI_3D_TX_PHY_SERCKCTRL 0x02
>>>>> +#define HDMI_3D_TX_PHY_SERCKKILLCTRL 0x03
>>>>> +#define HDMI_3D_TX_PHY_TXRESCTRL 0x04
>>>>> +#define HDMI_3D_TX_PHY_CKCALCTRL 0x05
>>>>> +#define HDMI_3D_TX_PHY_CPCE_CTRL 0x06
>>>>> +#define HDMI_3D_TX_PHY_TXCLKMEASCTRL 0x07
>>>>> +#define HDMI_3D_TX_PHY_TXMEASCTRL 0x08
>>>>> +#define HDMI_3D_TX_PHY_CKSYMTXCTRL 0x09
>>>>> +#define HDMI_3D_TX_PHY_CMPSEQCTRL 0x0a
>>>>> +#define HDMI_3D_TX_PHY_CMPPWRCTRL 0x0b
>>>>> +#define HDMI_3D_TX_PHY_CMPMODECTRL 0x0c
>>>>> +#define HDMI_3D_TX_PHY_MEASCTRL 0x0d
>>>>> +#define HDMI_3D_TX_PHY_VLEVCTRL 0x0e
>>>>> +#define HDMI_3D_TX_PHY_D2ACTRL 0x0f
>>>>> +#define HDMI_3D_TX_PHY_CURRCTRL 0x10
>>>>> +#define HDMI_3D_TX_PHY_DRVANACTRL 0x11
>>>>> +#define HDMI_3D_TX_PHY_PLLMEASCTRL 0x12
>>>>> +#define HDMI_3D_TX_PHY_PLLPHBYCTRL 0x13
>>>>> +#define HDMI_3D_TX_PHY_GRP_CTRL 0x14
>>>>> +#define HDMI_3D_TX_PHY_GMPCTRL 0x15
>>>>> +#define HDMI_3D_TX_PHY_MPLLMEASCTRL 0x16
>>>>> +#define HDMI_3D_TX_PHY_MSM_CTRL 0x17
>>>>> +#define HDMI_3D_TX_PHY_SCRPB_STATUS 0x18
>>>>> +#define HDMI_3D_TX_PHY_TXTERM 0x19
>>>>> +#define HDMI_3D_TX_PHY_PTRPT_ENBL 0x1a
>>>>> +#define HDMI_3D_TX_PHY_PATTERNGEN 0x1b
>>>>> +#define HDMI_3D_TX_PHY_SDCAP_MODE 0x1c
>>>>> +#define HDMI_3D_TX_PHY_SCOPEMODE 0x1d
>>>>> +#define HDMI_3D_TX_PHY_DIGTXMODE 0x1e
>>>>> +#define HDMI_3D_TX_PHY_STR_STATUS 0x1f
>>>>> +#define HDMI_3D_TX_PHY_SCOPECNT0 0x20
>>>>> +#define HDMI_3D_TX_PHY_SCOPECNT1 0x21
>>>>> +#define HDMI_3D_TX_PHY_SCOPECNT2 0x22
>>>>> +#define HDMI_3D_TX_PHY_SCOPECNTCLK 0x23
>>>>> +#define HDMI_3D_TX_PHY_SCOPESAMPLE 0x24
>>>>> +#define HDMI_3D_TX_PHY_SCOPECNTMSB01 0x25
>>>>> +#define HDMI_3D_TX_PHY_SCOPECNTMSB2CK 0x26
>>>>> +
>>>>> +/* HDMI_3D_TX_PHY_CKCALCTRL values */
>>>>> +#define HDMI_3D_TX_PHY_CKCALCTRL_OVERRIDE BIT(15)
>>>>> +
>>>>> +/* HDMI_3D_TX_PHY_MSM_CTRL values */
>>>>> +#define HDMI_3D_TX_PHY_MSM_CTRL_MPLL_PH_SEL_CK BIT(13)
>>>>> +#define HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_CLK_REF_MPLL (0 << 1)
>>>>> +#define HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_OFF (1 << 1)
>>>>> +#define HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_PCLK (2 << 1)
>>>>> +#define HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_FB_CLK (3 << 1)
>>>>> +#define HDMI_3D_TX_PHY_MSM_CTRL_SCOPE_CK_SEL BIT(0)
>>>>> +
>>>>> +/* HDMI_3D_TX_PHY_PTRPT_ENBL values */
>>>>> +#define HDMI_3D_TX_PHY_PTRPT_ENBL_OVERRIDE BIT(15)
>>>>> +#define HDMI_3D_TX_PHY_PTRPT_ENBL_PG_SKIP_BIT2 BIT(8)
>>>>> +#define HDMI_3D_TX_PHY_PTRPT_ENBL_PG_SKIP_BIT1 BIT(7)
>>>>> +#define HDMI_3D_TX_PHY_PTRPT_ENBL_PG_SKIP_BIT0 BIT(6)
>>>>> +#define HDMI_3D_TX_PHY_PTRPT_ENBL_CK_REF_ENB BIT(5)
>>>>> +#define HDMI_3D_TX_PHY_PTRPT_ENBL_RCAL_ENB BIT(4)
>>>>> +#define HDMI_3D_TX_PHY_PTRPT_ENBL_TX_CLK_ALIGN_ENB BIT(3)
>>>>> +#define HDMI_3D_TX_PHY_PTRPT_ENBL_TX_READY BIT(2)
>>>>> +#define HDMI_3D_TX_PHY_PTRPT_ENBL_CKO_WORD_ENB BIT(1)
>>>>> +#define HDMI_3D_TX_PHY_PTRPT_ENBL_REFCLK_ENB BIT(0)
>>>>> +
>>>>> #endif /* __DW_HDMI_H__ */
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