[PATCH 07/24] drm/bridge/sii8620: add support for burst eMSC transmissions

[Andrzej Hajda]

On 23.01.2017 09:20, Archit Taneja wrote:
(...)
>>  static void sii8620_fetch_edid(struct sii8620 *ctx)
>>  {
>>  	u8 lm_ddc, ddc_cmd, int3, cbus;
>> @@ -1041,7 +1181,7 @@ static int sii8620_wait_for_fsm_state(struct sii8620 *ctx, u8 state)
>>
>>  		if ((s & MSK_COC_STAT_0_FSM_STATE) == state)
>>  			return 0;
>> -		if (s & BIT_COC_STAT_0_PLL_LOCKED)
>> +		if (!(s & BIT_COC_STAT_0_PLL_LOCKED))
> Should this be a part of patch #5?

Yes, of course, it is just fix for patch #5.

>
>>  			return -EBUSY;
>>  		usleep_range(4000, 6000);
>>  	}
>> @@ -1417,6 +1557,19 @@ static void sii8620_irq_coc(struct sii8620 *ctx)
>>  {
>>  	u8 stat = sii8620_readb(ctx, REG_COC_INTR);
>>
>> +	if (stat & BIT_COC_CALIBRATION_DONE) {
>> +		u8 cstat = sii8620_readb(ctx, REG_COC_STAT_0);
>> +
>> +		cstat &= BIT_COC_STAT_0_PLL_LOCKED | MSK_COC_STAT_0_FSM_STATE;
>> +		if (cstat == (BIT_COC_STAT_0_PLL_LOCKED | 0x02)) {
>> +			sii8620_write_seq_static(ctx,
>> +				REG_COC_CTLB, 0,
>> +				REG_TRXINTMH, BIT_TDM_INTR_SYNC_DATA
>> +					      | BIT_TDM_INTR_SYNC_WAIT
>> +			);
>> +		}
>> +	}
>> +
>>  	sii8620_write(ctx, REG_COC_INTR, stat);
>>  }
>>
>> @@ -1507,6 +1660,41 @@ static void sii8620_irq_infr(struct sii8620 *ctx)
>>  		sii8620_start_video(ctx);
>>  }
>>
>> +static void sii8620_irq_tdm(struct sii8620 *ctx)
>> +{
>> +	u8 stat = sii8620_readb(ctx, REG_TRXINTH);
>> +	u8 tdm = sii8620_readb(ctx, REG_TRXSTA2);
>> +
>> +	if ((tdm & MSK_TDM_SYNCHRONIZED) == VAL_TDM_SYNCHRONIZED) {
>> +		ctx->mode = CM_ECBUS_S;
>> +		ctx->burst.rx_ack = 0;
>> +		ctx->burst.r_size = SII8620_BURST_BUF_LEN;
>> +		sii8620_burst_tx_rbuf_info(ctx, SII8620_BURST_BUF_LEN);
>> +		sii8620_mt_read_devcap(ctx, true);
>> +	} else {
>> +		sii8620_write_seq_static(ctx,
>> +			REG_MHL_PLL_CTL2, 0,
>> +			REG_MHL_PLL_CTL2, BIT_MHL_PLL_CTL2_CLKDETECT_EN
>> +		);
>> +	}
>> +
>> +	sii8620_write(ctx, REG_TRXINTH, stat);
>> +}
>> +
>> +static void sii8620_irq_block(struct sii8620 *ctx)
>> +{
>> +	u8 stat = sii8620_readb(ctx, REG_EMSCINTR);
>> +
>> +	if (stat & BIT_EMSCINTR_SPI_DVLD) {
>> +		u8 bstat = sii8620_readb(ctx, REG_SPIBURSTSTAT);
>> +
>> +		if (bstat & BIT_SPIBURSTSTAT_EMSC_NORMAL_MODE)
>> +			sii8620_burst_receive(ctx);
>> +	}
>> +
>> +	sii8620_write(ctx, REG_EMSCINTR, stat);
>> +}
>> +
>>  /* endian agnostic, non-volatile version of test_bit */
>>  static bool sii8620_test_bit(unsigned int nr, const u8 *addr)
>>  {
>> @@ -1522,8 +1710,10 @@ static irqreturn_t sii8620_irq_thread(int irq, void *data)
>>  		{ BIT_FAST_INTR_STAT_DISC, sii8620_irq_disc },
>>  		{ BIT_FAST_INTR_STAT_G2WB, sii8620_irq_g2wb },
>>  		{ BIT_FAST_INTR_STAT_COC, sii8620_irq_coc },
>> +		{ BIT_FAST_INTR_STAT_TDM, sii8620_irq_tdm },
>>  		{ BIT_FAST_INTR_STAT_MSC, sii8620_irq_msc },
>>  		{ BIT_FAST_INTR_STAT_MERR, sii8620_irq_merr },
>> +		{ BIT_FAST_INTR_STAT_BLOCK, sii8620_irq_block },
>>  		{ BIT_FAST_INTR_STAT_EDID, sii8620_irq_edid },
>>  		{ BIT_FAST_INTR_STAT_SCDT, sii8620_irq_scdt },
>>  		{ BIT_FAST_INTR_STAT_INFR, sii8620_irq_infr },
>> @@ -1539,7 +1729,9 @@ static irqreturn_t sii8620_irq_thread(int irq, void *data)
>>  		if (sii8620_test_bit(irq_vec[i].bit, stats))
>>  			irq_vec[i].handler(ctx);
>>
>> +	sii8620_burst_rx_all(ctx);
>>  	sii8620_mt_work(ctx);
>> +	sii8620_burst_send(ctx);
>>
>>  	ret = sii8620_clear_error(ctx);
>>  	if (ret) {
>> diff --git a/drivers/gpu/drm/bridge/sil-sii8620.h b/drivers/gpu/drm/bridge/sil-sii8620.h
>> index 3ee4e7e..f7bfbc3 100644
>> --- a/drivers/gpu/drm/bridge/sil-sii8620.h
>> +++ b/drivers/gpu/drm/bridge/sil-sii8620.h
>> @@ -403,12 +403,16 @@
>>
>>  /* TDM RX Status 2nd, default value: 0x00 */
>>  #define REG_TRXSTA2				0x015c
>> +#define MSK_TDM_SYNCHRONIZED			0xC0
> Would be nice to not have the hex digits in caps here.


OK, this one somehow sneaked out :)

Regards
Andrzej

>
> Thanks,
> Archit
>
>> +#define VAL_TDM_SYNCHRONIZED			0x80
>>
>>  /* TDM RX INT Low, default value: 0x00 */
>>  #define REG_TRXINTL				0x0163
>>
>>  /* TDM RX INT High, default value: 0x00 */
>>  #define REG_TRXINTH				0x0164
>> +#define BIT_TDM_INTR_SYNC_DATA			BIT(0)
>> +#define BIT_TDM_INTR_SYNC_WAIT			BIT(1)
>>
>>  /* TDM RX INTMASK High, default value: 0x00 */
>>  #define REG_TRXINTMH				0x0166
>>