[PATCH 4/8] ASoC: AMD: added condition checks for CZ specific code

[Mark Brown]

On Thu, Jun 29, 2017 at 12:58:02PM +0000, Mukunda, Vijendar wrote:

> -----Original Message-----
> From: Mark Brown [mailto:broonie at kernel.org] 
> Sent: Wednesday, June 28, 2017 11:36 PM
> To: Alex Deucher

Please fix your mail client to quote mails in a more normal fashion,
this looks pretty broken...

> >These defines are being added in the middle of a file but CHIP_STONEY is also used in another file in the previous patch (and apparently extensively throughout the DRM driver already).  This is obviously not good, >we shouldn't have multiple copies of the definition.

...especially in that it's reflowing the message it's replying to to
cause 80 column problems and has serious problems in that regard itself.

> We will modify code to use single definition for CHIP_STONEY and CHIP_CARRIZO.
> There are only two chip sets based on ACP 2.x design(Carrizo and Stoney).
> Our future Chip sets going to use different design based on next ACP IP version.

Write the code well, that way we don't have bad patterns in the codebase
and if plans change with regard to new variants you're covered.

> In the current patch, Condition checks added for Carrizo for setting SRAM BANK state.
> Memory Gating is disabled in Stoney,i.e SRAM Bank's won't be turned off. The default state for SRAM banks is ON.
> As Memory Gating is disabled, there is no need to add condition checks for Stoney to set SRAM Bank state.

Some documentation of this in the code would be good.
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