[radeon-alex:drm-next-4.12-wip 211/266] drivers/gpu/drm/amd/amdgpu/vega10_ih.c:106:82: warning: right shift count >= width of type

[kbuild test robot]

tree:   git://people.freedesktop.org/~agd5f/linux.git drm-next-4.12-wip
head:   ba92d1fc68425bbff454195c1a7bf07ec9b650d0
commit: 8ddf606557a311b7a4b4b5ad0578e52d2e7d5728 [211/266] drm/amdgpu: add vega10 interrupt handler
config: i386-allmodconfig (attached as .config)
compiler: gcc-6 (Debian 6.2.0-3) 6.2.0 20160901
reproduce:
        git checkout 8ddf606557a311b7a4b4b5ad0578e52d2e7d5728
        # save the attached .config to linux build tree
        make ARCH=i386 

All warnings (new ones prefixed by >>):

   In file included from drivers/gpu/drm/amd/amdgpu/vega10_ih.c:24:0:
   drivers/gpu/drm/amd/amdgpu/vega10_ih.c: In function 'vega10_ih_irq_init':
>> drivers/gpu/drm/amd/amdgpu/vega10_ih.c:106:82: warning: right shift count >= width of type [-Wshift-count-overflow]
      WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI), (adev->irq.ih.rb_dma_addr >> 40) &0xff);
                                                                                     ^
   drivers/gpu/drm/amd/amdgpu/amdgpu.h:1644:53: note: in definition of macro 'WREG32'
    #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0)
                                                        ^

vim +106 drivers/gpu/drm/amd/amdgpu/vega10_ih.c

    18	 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
    19	 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
    20	 * OTHER DEALINGS IN THE SOFTWARE.
    21	 *
    22	 */
    23	#include "drmP.h"
  > 24	#include "amdgpu.h"
    25	#include "amdgpu_ih.h"
    26	#include "soc15.h"
    27	
    28	
    29	#include "vega10/soc15ip.h"
    30	#include "vega10/OSSSYS/osssys_4_0_offset.h"
    31	#include "vega10/OSSSYS/osssys_4_0_sh_mask.h"
    32	
    33	#include "soc15_common.h"
    34	#include "vega10_ih.h"
    35	
    36	
    37	
    38	static void vega10_ih_set_interrupt_funcs(struct amdgpu_device *adev);
    39	
    40	/**
    41	 * vega10_ih_enable_interrupts - Enable the interrupt ring buffer
    42	 *
    43	 * @adev: amdgpu_device pointer
    44	 *
    45	 * Enable the interrupt ring buffer (VEGA10).
    46	 */
    47	static void vega10_ih_enable_interrupts(struct amdgpu_device *adev)
    48	{
    49		u32 ih_rb_cntl = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL));
    50	
    51		ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1);
    52		ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1);
    53		WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL), ih_rb_cntl);
    54		adev->irq.ih.enabled = true;
    55	}
    56	
    57	/**
    58	 * vega10_ih_disable_interrupts - Disable the interrupt ring buffer
    59	 *
    60	 * @adev: amdgpu_device pointer
    61	 *
    62	 * Disable the interrupt ring buffer (VEGA10).
    63	 */
    64	static void vega10_ih_disable_interrupts(struct amdgpu_device *adev)
    65	{
    66		u32 ih_rb_cntl = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL));
    67	
    68		ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0);
    69		ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0);
    70		WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL), ih_rb_cntl);
    71		/* set rptr, wptr to 0 */
    72		WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR), 0);
    73		WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR), 0);
    74		adev->irq.ih.enabled = false;
    75		adev->irq.ih.rptr = 0;
    76	}
    77	
    78	/**
    79	 * vega10_ih_irq_init - init and enable the interrupt ring
    80	 *
    81	 * @adev: amdgpu_device pointer
    82	 *
    83	 * Allocate a ring buffer for the interrupt controller,
    84	 * enable the RLC, disable interrupts, enable the IH
    85	 * ring buffer and enable it (VI).
    86	 * Called at device load and reume.
    87	 * Returns 0 for success, errors for failure.
    88	 */
    89	static int vega10_ih_irq_init(struct amdgpu_device *adev)
    90	{
    91		int ret = 0;
    92		int rb_bufsz;
    93		u32 ih_rb_cntl, ih_doorbell_rtpr;
    94		u32 tmp;
    95		u64 wptr_off;
    96	
    97		/* disable irqs */
    98		vega10_ih_disable_interrupts(adev);
    99	
   100		nbio_v6_1_ih_control(adev);
   101	
   102		ih_rb_cntl = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL));
   103		/* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/
   104		if (adev->irq.ih.use_bus_addr) {
   105			WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE), adev->irq.ih.rb_dma_addr >> 8);
 > 106			WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI), (adev->irq.ih.rb_dma_addr >> 40) &0xff);
   107			ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SPACE, 1);
   108		} else {
   109			WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE), adev->irq.ih.gpu_addr >> 8);

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