[PATCHv2 1/3] dt-bindings: display: Intel FPGA VIP drm driver Devicetree bindings

[Neil Armstrong]

On 04/25/2017 04:06 AM, hean.loong.ong at intel.com wrote:
> From: "Ong, Hean Loong" <hean.loong.ong at intel.com>
> 
> Device tree binding for Intel FPGA Video and Image
> Processing Suite. The binding involved would be generated
> from the Altera (Intel) Qsys system. The bindings would
> set the max width, max height, buts per pixel and memory
> port width. The device tree binding only supports the Intel
> Arria10 devkit and its variants. Vendor name retained as
> altr.
> 
> Signed-off-by: Ong, Hean Loong <hean.loong.ong at intel.com>
> ---
> v2:
> * Moved Device Tree bindings to Documentation/devicetree/bindings/display/
> * Added vendor name altr, to description
> ---
>  .../devicetree/bindings/display/altr,vip-fb2.txt   | 30 ++++++++++++++++++++++
>  1 file changed, 30 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/display/altr,vip-fb2.txt
> 
> diff --git a/Documentation/devicetree/bindings/display/altr,vip-fb2.txt b/Documentation/devicetree/bindings/display/altr,vip-fb2.txt
> new file mode 100644
> index 0000000..bdffefb
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/altr,vip-fb2.txt
> @@ -0,0 +1,30 @@
> +Intel Video and Image Processing(VIP) Frame Buffer II bindings
> +
> +Supported hardware: Arria 10 and above with display port IP
> +

Hi,

> +The drm driver for the Arria 10 devkit would require the display resolution
> +and pixel information to be included as these values are generated based
> +on the FPGA design that drives the video connector attached to the drm driver
> +Information the FPGA video IP component can be acquired from
> +https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug_vip.pdf

The bindings should not reference the driver, but only the hardware and the way it is configured
and interconnected with the system.
Please explicit that this is an IP component that can be configured with explicit limits on
the display widths and heights and memory parameters.

But you should also indicate over what this IP is connected and add a port connected to a connector
node in case this ip is not used on a specific board like in [1] or [2] :

"""
Required nodes:

The connections to the DU output video ports are modeled using the OF graph
bindings specified in Documentation/devicetree/bindings/graph.txt.

The following table lists for each supported model the port number
corresponding to each DU output.

		Port 0		Port1		Port2		Port3
-----------------------------------------------------------------------------
 R8A7779 (H1)	DPAD 0		DPAD 1		-		-
"""

You may also need to add a "Display Port" connector binding aswell along the HDMI, VGA, ....

I know this targets an FPGA system, so you should explicit that in the description.

> +Required properties:
> +
> +- compatible: "altr,vip-frame-buffer-2.0"

You should also add model specific compatible strings for each supported FPGA devices.

> +- reg: Physical base address and length of the framebuffer controller's
> +  registers.
> +- altr,max-width: The width of the framebuffer in pixels.
> +- altr,max-height: The height of the framebuffer in pixels.
> +- altr,bits-per-symbol: only "8" is currently supported
> +- altr,mem-port-width = the bus width of the avalon master port on the frame reader

What is the avalon master port ?
Can you add a schema to explicit how this IP is connected to the system ?

> +
> +Example:
> +
> +	dp_0_frame_buf: vip at 100000280 {
> +			compatible = "altr,vip-frame-buffer-2.0";
> +			reg = <0x00000001 0x00000280 0x00000040>;
> +			altr,max-width = <1280>;
> +			altr,max-height = <720>;
> +			altr,bits-per-symbol = <8>;
> +			altr,mem-port-width = <128>;
> +	};
> 


[1] Documentation/devicetree/bindings/display/amlogic,meson-vpu.txt
[2] Documentation/devicetree/bindings/display/renesas,du.txt

Thanks,

Neil