[PATCHv2 0/3] Intel FPGA VIP Frame Buffer II DRM Driver

[Daniel Vetter]

On Wed, May 3, 2017 at 10:28 PM, Eric Anholt <eric at anholt.net> wrote:
>> From: Ong Hean Loong <hean.loong.ong at intel.com>
>>
>> Hi,
>>
>> The new Intel Arria10 SOC FPGA devkit has a Display Port IP component
>> which requires a new driver. This is a virtual driver in which the
>> FGPA hardware would enable the Display Port based on the information
>> and data provided from the DRM frame buffer from the OS. Basically all
>> all information with reagrds to resolution and bits per pixel are
>> pre-configured on the FPGA design and these information are fed to
>> the driver via the device tree information as part of the hardware
>> information.
>
> I started reviewing the code, but I want to make sure I understand
> what's going on:
>
> This IP core isn't displaying contents from system memory on some sort
> of actual physical display, right?  It's a core that takes some input
> video stream (not described in the DT or in this driver) and stores it
> to memory?

I assumed it's the input IP core in the linked pdf, i.e. the CVI
(clocked video input). There's also a CVO (clocked video output), and
that would indeed be a misfit for drm. Definitely need to clarify this
(in the DT description).
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch