[PATCH 4/6] drm/omap: remove read_irqenable()

[Laurent Pinchart]

Hi Tomi,

Thank you for the patch.

On Thursday 27 Apr 2017 13:27:52 Tomi Valkeinen wrote:
> We only use read_irqenable() to flush posted write. Instead of having a
> separate function for this, do the flush implicitly in write_irqenable().
> Thus we can remove read_irqenable().
> 
> Signed-off-by: Tomi Valkeinen <tomi.valkeinen at ti.com>

Reviewed-by: Laurent Pinchart <laurent.pinchart at ideasonboard.com>

> ---
>  drivers/gpu/drm/omapdrm/dss/dispc.c   | 9 +++------
>  drivers/gpu/drm/omapdrm/dss/omapdss.h | 1 -
>  drivers/gpu/drm/omapdrm/omap_irq.c    | 1 -
>  3 files changed, 3 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/omapdrm/dss/dispc.c
> b/drivers/gpu/drm/omapdrm/dss/dispc.c index 97f4a1163fbe..352fad583571
> 100644
> --- a/drivers/gpu/drm/omapdrm/dss/dispc.c
> +++ b/drivers/gpu/drm/omapdrm/dss/dispc.c
> @@ -3782,11 +3782,6 @@ static void dispc_clear_irqstatus(u32 mask)
>  	dispc_write_reg(DISPC_IRQSTATUS, mask);
>  }
> 
> -static u32 dispc_read_irqenable(void)
> -{
> -	return dispc_read_reg(DISPC_IRQENABLE);
> -}
> -
>  static void dispc_write_irqenable(u32 mask)
>  {
>  	u32 old_mask = dispc_read_reg(DISPC_IRQENABLE);
> @@ -3795,6 +3790,9 @@ static void dispc_write_irqenable(u32 mask)
>  	dispc_clear_irqstatus((mask ^ old_mask) & mask);
> 
>  	dispc_write_reg(DISPC_IRQENABLE, mask);
> +
> +	/* flush posted write */
> +	dispc_read_reg(DISPC_IRQENABLE);
>  }
> 
>  void dispc_enable_sidle(void)
> @@ -4345,7 +4343,6 @@ static void dispc_errata_i734_wa(void)
>  static const struct dispc_ops dispc_ops = {
>  	.read_irqstatus = dispc_read_irqstatus,
>  	.clear_irqstatus = dispc_clear_irqstatus,
> -	.read_irqenable = dispc_read_irqenable,
>  	.write_irqenable = dispc_write_irqenable,
> 
>  	.request_irq = dispc_request_irq,
> diff --git a/drivers/gpu/drm/omapdrm/dss/omapdss.h
> b/drivers/gpu/drm/omapdrm/dss/omapdss.h index a2b9b7f29472..44bf53351e00
> 100644
> --- a/drivers/gpu/drm/omapdrm/dss/omapdss.h
> +++ b/drivers/gpu/drm/omapdrm/dss/omapdss.h
> @@ -881,7 +881,6 @@ void dss_mgr_unregister_framedone_handler(enum
> omap_channel channel, struct dispc_ops {
>  	u32 (*read_irqstatus)(void);
>  	void (*clear_irqstatus)(u32 mask);
> -	u32 (*read_irqenable)(void);
>  	void (*write_irqenable)(u32 mask);
> 
>  	int (*request_irq)(irq_handler_t handler, void *dev_id);
> diff --git a/drivers/gpu/drm/omapdrm/omap_irq.c
> b/drivers/gpu/drm/omapdrm/omap_irq.c index 115104cdcc59..7afe4b90befd
> 100644
> --- a/drivers/gpu/drm/omapdrm/omap_irq.c
> +++ b/drivers/gpu/drm/omapdrm/omap_irq.c
> @@ -41,7 +41,6 @@ static void omap_irq_update(struct drm_device *dev)
>  	DBG("irqmask=%08x", irqmask);
> 
>  	priv->dispc_ops->write_irqenable(irqmask);
> -	priv->dispc_ops->read_irqenable();        /* flush posted write */
>  }
> 
>  static void omap_irq_wait_handler(struct omap_irq_wait *wait)

-- 
Regards,

Laurent Pinchart