[PATCH v2] drm/pl111: Register the clock divider and use it.

[Linus Walleij]

On Mon, May 8, 2017 at 9:33 PM, Eric Anholt <eric at anholt.net> wrote:

> This is required for the panel to work on bcm911360, where CLCDCLK is
> the fixed 200Mhz AXI41 clock.  The rate set is still passed up to the
> CLCDCLK, for platforms that have a settable rate on that one.
>
> v2: Set SET_RATE_PARENT (caught by Linus Walleij), depend on
>     COMMON_CLK.
>
> Signed-off-by: Eric Anholt <eric at anholt.net>

Reviewed-by: Linus Walleij <linus.walleij at linaro.org>

Yours,
Linus Walleij