[PATCH v2] drm/pl111: Register the clock divider and use it.

[Linus Walleij]

On Tue, May 9, 2017 at 8:18 PM, Eric Anholt <eric at anholt.net> wrote:
> Linus Walleij <linus.walleij at linaro.org> writes:
>
>> On Mon, May 8, 2017 at 9:33 PM, Eric Anholt <eric at anholt.net> wrote:
>>
>>> This is required for the panel to work on bcm911360, where CLCDCLK is
>>> the fixed 200Mhz AXI41 clock.  The rate set is still passed up to the
>>> CLCDCLK, for platforms that have a settable rate on that one.
>>>
>>> v2: Set SET_RATE_PARENT (caught by Linus Walleij), depend on
>>>     COMMON_CLK.
>>>
>>> Signed-off-by: Eric Anholt <eric at anholt.net>
>>
>> Reviewed-by: Linus Walleij <linus.walleij at linaro.org>
>
> Thanks.  Waiting on an ack from clock folks, then we'll be ready to go,
> I think.

Mike/Stephen?

It would be nice to have this queued in -next quite early in the v4.13
development cycle, so I can start looking into migrating the rest of the
old fbdev users to this.

BCM911360 seems like some oddity, there is not even a pictur of
it online, but I guess it's a cool little gadget :)

Yours,
Linus Walleij