[PATCH 0/3] Adding new drm formats needed by Xilinx IPs

[Emil Velikov]

On 28 November 2017 at 11:09, Daniel Vetter <daniel at ffwll.ch> wrote:
> On Mon, Nov 27, 2017 at 06:27:30PM -0800, Hyun Kwon wrote:
>> Hi,
>>
>> This series is to add new drm formats needed by some Xilinx IPs.
>> Some formats have unique characteristics such as pixels not being
>> byte-aligned. For instance, some 10bit formats have 2bit padding
>> after every 3-10bit components:
>>
>>       32b[0]: 10b comp0 - 10b comp1 - 10b comp2 - 2b padding
>>       32b[1]: 10b comp3 - 10b comp4 - 10b comp5 - 2b padding
>>       ...
>>
>> To model this, additional information is added to struct drm_format_info.
>> The patch has been tested with downstream drivers as well as the downstream
>> user space component (ex, modified modetest).
>>
>> Thanks,
>> hyun
>>
>> Jeffrey Mouroux (2):
>>   uapi: drm: New fourcc codes needed by Xilinx Video IP
>>   drm: fourcc: Update DRM Framework with new fourcc codes
>>
>> Satish Kumar Nagireddy (1):
>>   drm: drm_fourcc: Add scaling and padding factor to drm_format_info
>
> We need the driver for this.

To elaborate this in different light:
Without an upstream user (both kernel and userspace) this will be in a
perpetual broken state.
If the Xilinx DRM driver is still far off, one could update any of the
existing drivers - say i915 :-P

HTH
Emil