[radeon-alex:amd-staging-drm-next 1172/1179] drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/rv_hwmgr.c:424:44: error: passing argument 1 of 'smum_send_msg_to_smc' from incompatible pointer type

kbuild test robot fengguang.wu at intel.com
Wed Oct 4 00:11:56 UTC 2017


tree:   git://people.freedesktop.org/~agd5f/linux.git amd-staging-drm-next
head:   ea0eda9a882b5df33808dbd85bd64376ed187618
commit: cf5235684f9736278f395d1668876000490120d2 [1172/1179] drm/amd/powerplay: get raven max/min gfx clocks
config: ia64-allmodconfig (attached as .config)
compiler: ia64-linux-gcc (GCC) 6.2.0
reproduce:
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        git checkout cf5235684f9736278f395d1668876000490120d2
        # save the attached .config to linux build tree
        make.cross ARCH=ia64 

Note: the radeon-alex/amd-staging-drm-next HEAD ea0eda9a882b5df33808dbd85bd64376ed187618 builds fine.
      It only hurts bisectibility.

All errors (new ones prefixed by >>):

   In file included from drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/rv_hwmgr.c:23:0:
   drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/rv_hwmgr.c: In function 'rv_populate_clock_table':
>> drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/rv_hwmgr.c:424:44: error: passing argument 1 of 'smum_send_msg_to_smc' from incompatible pointer type [-Werror=incompatible-pointer-types]
     PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr->smumgr,
                                               ^
   drivers/gpu/drm/amd/amdgpu/../powerplay/inc/pp_debug.h:39:9: note: in definition of macro 'PP_ASSERT_WITH_CODE'
      if (!(cond)) {   \
            ^~~~
   In file included from drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/rv_hwmgr.c:31:0:
   drivers/gpu/drm/amd/amdgpu/../powerplay/inc/smumgr.h:99:12: note: expected 'struct pp_hwmgr *' but argument is of type 'struct pp_smumgr *'
    extern int smum_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg);
               ^~~~~~~~~~~~~~~~~~~~
   In file included from drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/rv_hwmgr.c:23:0:
>> drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/rv_hwmgr.c:428:44: error: passing argument 1 of 'rv_read_arg_from_smc' from incompatible pointer type [-Werror=incompatible-pointer-types]
     PP_ASSERT_WITH_CODE(!rv_read_arg_from_smc(hwmgr->smumgr,
                                               ^
   drivers/gpu/drm/amd/amdgpu/../powerplay/inc/pp_debug.h:39:9: note: in definition of macro 'PP_ASSERT_WITH_CODE'
      if (!(cond)) {   \
            ^~~~
   In file included from drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/rv_hwmgr.c:37:0:
   drivers/gpu/drm/amd/amdgpu/../powerplay/smumgr/rv_smumgr.h:54:5: note: expected 'struct pp_hwmgr *' but argument is of type 'struct pp_smumgr *'
    int rv_read_arg_from_smc(struct pp_hwmgr *hwmgr, uint32_t *arg);
        ^~~~~~~~~~~~~~~~~~~~
   In file included from drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/rv_hwmgr.c:23:0:
   drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/rv_hwmgr.c:434:44: error: passing argument 1 of 'smum_send_msg_to_smc' from incompatible pointer type [-Werror=incompatible-pointer-types]
     PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr->smumgr,
                                               ^
   drivers/gpu/drm/amd/amdgpu/../powerplay/inc/pp_debug.h:39:9: note: in definition of macro 'PP_ASSERT_WITH_CODE'
      if (!(cond)) {   \
            ^~~~
   In file included from drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/rv_hwmgr.c:31:0:
   drivers/gpu/drm/amd/amdgpu/../powerplay/inc/smumgr.h:99:12: note: expected 'struct pp_hwmgr *' but argument is of type 'struct pp_smumgr *'
    extern int smum_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg);
               ^~~~~~~~~~~~~~~~~~~~
   In file included from drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/rv_hwmgr.c:23:0:
   drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/rv_hwmgr.c:438:44: error: passing argument 1 of 'rv_read_arg_from_smc' from incompatible pointer type [-Werror=incompatible-pointer-types]
     PP_ASSERT_WITH_CODE(!rv_read_arg_from_smc(hwmgr->smumgr,
                                               ^
   drivers/gpu/drm/amd/amdgpu/../powerplay/inc/pp_debug.h:39:9: note: in definition of macro 'PP_ASSERT_WITH_CODE'
      if (!(cond)) {   \
            ^~~~
   In file included from drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/rv_hwmgr.c:37:0:
   drivers/gpu/drm/amd/amdgpu/../powerplay/smumgr/rv_smumgr.h:54:5: note: expected 'struct pp_hwmgr *' but argument is of type 'struct pp_smumgr *'
    int rv_read_arg_from_smc(struct pp_hwmgr *hwmgr, uint32_t *arg);
        ^~~~~~~~~~~~~~~~~~~~
   cc1: some warnings being treated as errors

vim +/smum_send_msg_to_smc +424 drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/rv_hwmgr.c

   376	
   377	
   378	static int rv_populate_clock_table(struct pp_hwmgr *hwmgr)
   379	{
   380		int result;
   381	
   382		struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend);
   383		DpmClocks_t  *table = &(rv_data->clock_table);
   384		struct rv_clock_voltage_information *pinfo = &(rv_data->clock_vol_info);
   385	
   386		result = rv_copy_table_from_smc(hwmgr, (uint8_t *)table, CLOCKTABLE);
   387	
   388		PP_ASSERT_WITH_CODE((0 == result),
   389				"Attempt to copy clock table from smc failed",
   390				return result);
   391	
   392		if (0 == result && table->DcefClocks[0].Freq != 0) {
   393			rv_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_dcefclk,
   394							NUM_DCEFCLK_DPM_LEVELS,
   395							&rv_data->clock_table.DcefClocks[0]);
   396			rv_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_socclk,
   397							NUM_SOCCLK_DPM_LEVELS,
   398							&rv_data->clock_table.SocClocks[0]);
   399			rv_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_fclk,
   400							NUM_FCLK_DPM_LEVELS,
   401							&rv_data->clock_table.FClocks[0]);
   402			rv_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_mclk,
   403							NUM_MEMCLK_DPM_LEVELS,
   404							&rv_data->clock_table.MemClocks[0]);
   405		} else {
   406			rv_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_dcefclk,
   407							ARRAY_SIZE(VddDcfClk),
   408							&VddDcfClk[0]);
   409			rv_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_socclk,
   410							ARRAY_SIZE(VddSocClk),
   411							&VddSocClk[0]);
   412			rv_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_fclk,
   413							ARRAY_SIZE(VddFClk),
   414							&VddFClk[0]);
   415		}
   416		rv_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_dispclk,
   417						ARRAY_SIZE(VddDispClk),
   418						&VddDispClk[0]);
   419		rv_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_dppclk,
   420						ARRAY_SIZE(VddDppClk), &VddDppClk[0]);
   421		rv_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_phyclk,
   422						ARRAY_SIZE(VddPhyClk), &VddPhyClk[0]);
   423	
 > 424		PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr->smumgr,
   425				PPSMC_MSG_GetMinGfxclkFrequency),
   426				"Attempt to get min GFXCLK Failed!",
   427				return -1);
 > 428		PP_ASSERT_WITH_CODE(!rv_read_arg_from_smc(hwmgr->smumgr,
   429				&result),
   430				"Attempt to get min GFXCLK Failed!",
   431				return -1);
   432		rv_data->gfx_min_freq_limit = result * 100;
   433	
   434		PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr->smumgr,
   435				PPSMC_MSG_GetMaxGfxclkFrequency),
   436				"Attempt to get max GFXCLK Failed!",
   437				return -1);
   438		PP_ASSERT_WITH_CODE(!rv_read_arg_from_smc(hwmgr->smumgr,
   439				&result),
   440				"Attempt to get max GFXCLK Failed!",
   441				return -1);
   442		rv_data->gfx_max_freq_limit = result * 100;
   443	
   444		return 0;
   445	}
   446	

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation
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