[PATCH v6 1/2] drm_fourcc: Add new P010, P016 video format
Tapani Pälli
tapani.palli at intel.com
Tue Oct 24 06:30:57 UTC 2017
On 10/17/2017 02:43 PM, ayaka wrote:
>
>
> On 10/12/2017 07:56 PM, Tapani Pälli wrote:
>> Is this one going to land soon? The discussion was a bit hard to read
>> but it looks like in the end consensus was that everything looks good
>> in this patch.
> I am very sorry, I am too busy with the other dma problem in rockchip.
> The main problem is that none of the driver have used those format.
> Although the rockchip vop supports 10 bit pixel format but not the p010.
OK no worries, I thought these formats are already used by some driver.
>>
>> Thanks;
>>
>>
>> On 03/01/2017 01:21 AM, clinton.a.taylor at intel.com wrote:
>>> From: Clint Taylor <clinton.a.taylor at intel.com>
>>>
>>> P010 is a planar 4:2:0 YUV with interleaved UV plane, 10 bits per
>>> channel video format. Rockchip's vop support this video format(little
>>> endian only) as the input video format.
>>>
>>> P016 is a planar 4:2:0 YUV 12 bits per channel
>>>
>>> P016 is a planar 4:2:0 YUV with interleaved UV plane, 16 bits per
>>> channel video format.
>>>
>>> V3: Added P012 and fixed cpp for P010
>>> V4: format definition refined per review
>>> V5: Format comment block for each new pixel format
>>> V6: reversed Cb/Cr order in comments
>>>
>>> Cc: Daniel Stone <daniel at fooishbar.org>
>>> Cc: Ville Syrjälä <ville.syrjala at linux.intel.com>
>>>
>>> Signed-off-by: Randy Li <ayaka at soulik.info>
>>> Signed-off-by: Clint Taylor <clinton.a.taylor at intel.com>
>>> ---
>>> drivers/gpu/drm/drm_fourcc.c | 3 +++
>>> include/uapi/drm/drm_fourcc.h | 21 +++++++++++++++++++++
>>> 2 files changed, 24 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
>>> index 90d2cc8..3e0fd58 100644
>>> --- a/drivers/gpu/drm/drm_fourcc.c
>>> +++ b/drivers/gpu/drm/drm_fourcc.c
>>> @@ -165,6 +165,9 @@ const struct drm_format_info
>>> *__drm_format_info(u32 format)
>>> { .format = DRM_FORMAT_UYVY, .depth = 0, .num_planes
>>> = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1 },
>>> { .format = DRM_FORMAT_VYUY, .depth = 0, .num_planes
>>> = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1 },
>>> { .format = DRM_FORMAT_AYUV, .depth = 0, .num_planes
>>> = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1 },
>>> + { .format = DRM_FORMAT_P010, .depth = 0, .num_planes
>>> = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2 },
>>> + { .format = DRM_FORMAT_P012, .depth = 0, .num_planes
>>> = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2 },
>>> + { .format = DRM_FORMAT_P016, .depth = 0, .num_planes
>>> = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2 },
>>> };
>>> unsigned int i;
>>> diff --git a/include/uapi/drm/drm_fourcc.h
>>> b/include/uapi/drm/drm_fourcc.h
>>> index ef20abb..762646d 100644
>>> --- a/include/uapi/drm/drm_fourcc.h
>>> +++ b/include/uapi/drm/drm_fourcc.h
>>> @@ -128,6 +128,27 @@
>>> #define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /*
>>> non-subsampled Cb:Cr plane */
>>> /*
>>> + * 2 plane YCbCr MSB aligned
>>> + * index 0 = Y plane, [15:0] Y:x [10:6] little endian
>>> + * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian
>>> + */
>>> +#define DRM_FORMAT_P010 fourcc_code('P', '0', '1', '0') /*
>>> 2x2 subsampled Cr:Cb plane 10 bits per channel */
>>> +
>>> +/*
>>> + * 2 plane YCbCr MSB aligned
>>> + * index 0 = Y plane, [15:0] Y:x [12:4] little endian
>>> + * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [12:4:12:4] little endian
>>> + */
>>> +#define DRM_FORMAT_P012 fourcc_code('P', '0', '1', '2') /*
>>> 2x2 subsampled Cr:Cb plane 12 bits per channel */
>>> +
>>> +/*
>>> + * 2 plane YCbCr MSB aligned
>>> + * index 0 = Y plane, [15:0] Y little endian
>>> + * index 1 = Cr:Cb plane, [31:0] Cr:Cb [16:16] little endian
>>> + */
>>> +#define DRM_FORMAT_P016 fourcc_code('P', '0', '1', '6') /*
>>> 2x2 subsampled Cr:Cb plane 16 bits per channel */
>>> +
>>> +/*
>>> * 3 plane YCbCr
>>> * index 0: Y plane, [7:0] Y
>>> * index 1: Cb plane, [7:0] Cb
>>>
>
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