[PATCH v6 1/2] drm/bridge: Add Cadence DSI driver
Archit Taneja
architt at codeaurora.org
Sun Apr 15 08:09:44 UTC 2018
Hi,
On Tuesday 10 April 2018 06:30 PM, Boris Brezillon wrote:
> From: Boris Brezillon <boris.brezillon at free-electrons.com>
>
> Add a driver for Cadence DPI -> DSI bridge.
>
> This driver only support a subset of Cadence DSI bridge capabilities.
>
> This driver has been tested/debugged in a simulated environment which
> explains why some of the features are missing. Here is a
> non-exhaustive list of missing features:
> * burst mode
> * DPHY init/configuration steps
> * support for additional input interfaces (SDI input)
>
> DSI commands and non-burst video mode have been tested.
>
> Signed-off-by: Boris Brezillon <boris.brezillon at free-electrons.com>
> Reviewed-by: Andrzej Hajda <a.hajda at samsung.com>
> Acked-by: Eric Anholt <eric at anholt.net>
> ---
> Hello,
>
> This version is still missing DPHY config/init code, mainly because I
> don't have a DPHY (either real or emulated) to test with. But I'm
> working on a DPHY abstraction layer to help extract common DPHY
> operations out of DSI drivers so that DPHY drivers can be used outside
> of the DRM world (I know D-PHYs can be used with CSI which belongs in
> V4L).
>
> Regards,
>
> Boris
>
> This version is still missing
>
> Changes in v6:
> - Use SPDX header
> - Do not enable the sys_clk in the probe function
> - Remove unneeded udelay()
> - Add a function to make sure the PLL and pixel clock are close enough
> to be recoverable if they don't match exactly
> - Add the DPHY init sequence used in simulation (likely to be different
> based on each SoC integration)
>
> Changes in v5:
> - Add runtime PM support
>
> Changes in v4:
> - Fix typos
> - Rename clks as suggested by Tomi
> - Fix DSI setup done in cdns_dsi_bridge_enable()
> - Add a precision about where this bridge is supposed to used to the
> Kconfig entry
> - Let DRM_CDNS_DSI select DRM_PANEL_BRIDGE
> - Remove the IP version from the DT compatible name
> - Adapt register the layout to match the one used in the last revision
> of the IP (hopefully the final version)
>
> Changes in v3:
> - replace magic values by real timing calculation. The DPHY PLL clock
> is still hardcoded since we don't have a working DPHY block yet, and
> this is the piece of HW we need to dynamically configure the PLL
> rate based on the display refresh rate and the resolution.
> - parse DSI devices represented with the OF-graph. This is needed to
> support DSI devices controlled through an external bus like I2C or
> SPI.
> - use the DRM panel-bridge infrastructure to simplify the DRM panel
> logic
>
> Changes in v2:
> - rebase on v4.12-rc1 and adapt to driver to the drm_bridge API changes
> - return the correct error when devm_clk_get(sysclk) fails
> - add missing depends on OF and select DRM_PANEL in the Kconfig entry
>
> DSI runtime PM
> ---
> drivers/gpu/drm/bridge/Kconfig | 10 +
> drivers/gpu/drm/bridge/Makefile | 1 +
> drivers/gpu/drm/bridge/cdns-dsi.c | 1624 +++++++++++++++++++++++++++++++++++++
> 3 files changed, 1635 insertions(+)
> create mode 100644 drivers/gpu/drm/bridge/cdns-dsi.c
>
> diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
> index 3aa65bdecb0e..1cd267880b53 100644
> --- a/drivers/gpu/drm/bridge/Kconfig
> +++ b/drivers/gpu/drm/bridge/Kconfig
> @@ -25,6 +25,16 @@ config DRM_ANALOGIX_ANX78XX
> the HDMI output of an application processor to MyDP
> or DisplayPort.
>
> +config DRM_CDNS_DSI
> + tristate "Cadence DPI/DSI bridge"
> + select DRM_KMS_HELPER
> + select DRM_MIPI_DSI
> + select DRM_PANEL_BRIDGE
> + depends on OF
> + help
> + Support Cadence DPI to DSI bridge. This is an internal
> + bridge and is meant to be directly embedded in a SoC.
> +
> config DRM_DUMB_VGA_DAC
> tristate "Dumb VGA DAC Bridge support"
> depends on OF
> diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
> index 373eb28f31ed..aea7cbe9070b 100644
> --- a/drivers/gpu/drm/bridge/Makefile
> +++ b/drivers/gpu/drm/bridge/Makefile
> @@ -1,5 +1,6 @@
> # SPDX-License-Identifier: GPL-2.0
> obj-$(CONFIG_DRM_ANALOGIX_ANX78XX) += analogix-anx78xx.o
> +obj-$(CONFIG_DRM_CDNS_DSI) += cdns-dsi.o
> obj-$(CONFIG_DRM_DUMB_VGA_DAC) += dumb-vga-dac.o
> obj-$(CONFIG_DRM_LVDS_ENCODER) += lvds-encoder.o
> obj-$(CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW) += megachips-stdpxxxx-ge-b850v3-fw.o
> diff --git a/drivers/gpu/drm/bridge/cdns-dsi.c b/drivers/gpu/drm/bridge/cdns-dsi.c
> new file mode 100644
> index 000000000000..d4ceb961f475
> --- /dev/null
> +++ b/drivers/gpu/drm/bridge/cdns-dsi.c
> @@ -0,0 +1,1624 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright: 2017 Cadence Design Systems, Inc.
> + *
> + * Author: Boris Brezillon <boris.brezillon at free-electrons.com>
> + */
> +
> +#include <drm/drm_atomic_helper.h>
> +#include <drm/drm_bridge.h>
> +#include <drm/drm_crtc_helper.h>
> +#include <drm/drm_mipi_dsi.h>
> +#include <drm/drm_panel.h>
> +#include <video/mipi_display.h>
> +
> +#include <linux/clk.h>
> +#include <linux/iopoll.h>
> +#include <linux/module.h>
> +#include <linux/of_address.h>
> +#include <linux/of_graph.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/reset.h>
> +
> +#define IP_CONF 0x0
> +#define SP_HS_FIFO_DEPTH(x) (((x) & GENMASK(30, 26)) >> 26)
> +#define SP_LP_FIFO_DEPTH(x) (((x) & GENMASK(25, 21)) >> 21)
> +#define VRS_FIFO_DEPTH(x) (((x) & GENMASK(20, 16)) >> 16)
> +#define DIRCMD_FIFO_DEPTH(x) (((x) & GENMASK(15, 13)) >> 13)
> +#define SDI_IFACE_32 BIT(12)
> +#define INTERNAL_DATAPATH_32 (0 << 10)
> +#define INTERNAL_DATAPATH_16 (1 << 10)
> +#define INTERNAL_DATAPATH_8 (3 << 10)
> +#define INTERNAL_DATAPATH_SIZE ((x) & GENMASK(11, 10))
> +#define NUM_IFACE(x) ((((x) & GENMASK(9, 8)) >> 8) + 1)
> +#define MAX_LANE_NB(x) (((x) & GENMASK(7, 6)) >> 6)
> +#define RX_FIFO_DEPTH(x) ((x) & GENMASK(5, 0))
> +
> +#define MCTL_MAIN_DATA_CTL 0x4
> +#define TE_MIPI_POLLING_EN BIT(25)
> +#define TE_HW_POLLING_EN BIT(24)
> +#define DISP_EOT_GEN BIT(18)
> +#define HOST_EOT_GEN BIT(17)
> +#define DISP_GEN_CHECKSUM BIT(16)
> +#define DISP_GEN_ECC BIT(15)
> +#define BTA_EN BIT(14)
> +#define READ_EN BIT(13)
> +#define REG_TE_EN BIT(12)
> +#define IF_TE_EN(x) BIT(8 + (x))
> +#define TVG_SEL BIT(6)
> +#define VID_EN BIT(5)
> +#define IF_VID_SELECT(x) ((x) << 2)
> +#define IF_VID_SELECT_MASK GENMASK(3, 2)
> +#define IF_VID_MODE BIT(1)
> +#define LINK_EN BIT(0)
> +
> +#define MCTL_MAIN_PHY_CTL 0x8
> +#define HS_INVERT_DAT(x) BIT(19 + ((x) * 2))
> +#define SWAP_PINS_DAT(x) BIT(18 + ((x) * 2))
> +#define HS_INVERT_CLK BIT(17)
> +#define SWAP_PINS_CLK BIT(16)
> +#define HS_SKEWCAL_EN BIT(15)
> +#define WAIT_BURST_TIME(x) ((x) << 10)
> +#define DATA_ULPM_EN(x) BIT(6 + (x))
> +#define CLK_ULPM_EN BIT(5)
> +#define CLK_CONTINUOUS BIT(4)
> +#define DATA_LANE_EN(x) BIT((x) - 1)
> +
> +#define MCTL_MAIN_EN 0xc
> +#define DATA_FORCE_STOP BIT(17)
> +#define CLK_FORCE_STOP BIT(16)
> +#define IF_EN(x) BIT(13 + (x))
> +#define DATA_LANE_ULPM_REQ(l) BIT(9 + (l))
> +#define CLK_LANE_ULPM_REQ BIT(8)
> +#define DATA_LANE_START(x) BIT(4 + (x))
> +#define CLK_LANE_EN BIT(3)
> +#define PLL_START BIT(0)
> +
> +#define MCTL_DPHY_CFG0 0x10
> +#define DPHY_C_RSTB BIT(20)
> +#define DPHY_D_RSTB(x) GENMASK(15 + (x), 16)
> +#define DPHY_PLL_PDN BIT(10)
> +#define DPHY_CMN_PDN BIT(9)
> +#define DPHY_C_PDN BIT(8)
> +#define DPHY_D_PDN(x) GENMASK(3 + (x), 4)
> +#define DPHY_ALL_D_PDN GENMASK(7, 4)
> +#define DPHY_PLL_PSO BIT(1)
> +#define DPHY_CMN_PSO BIT(0)
> +
> +#define MCTL_DPHY_TIMEOUT1 0x14
> +#define HSTX_TIMEOUT(x) ((x) << 4)
> +#define HSTX_TIMEOUT_MAX GENMASK(17, 0)
> +#define CLK_DIV(x) (x)
> +#define CLK_DIV_MAX GENMASK(3, 0)
> +
> +#define MCTL_DPHY_TIMEOUT2 0x18
> +#define LPRX_TIMEOUT(x) (x)
> +
> +#define MCTL_ULPOUT_TIME 0x1c
> +#define DATA_LANE_ULPOUT_TIME(x) ((x) << 9)
> +#define CLK_LANE_ULPOUT_TIME(x) (x)
> +
> +#define MCTL_3DVIDEO_CTL 0x20
> +#define VID_VSYNC_3D_EN BIT(7)
> +#define VID_VSYNC_3D_LR BIT(5)
> +#define VID_VSYNC_3D_SECOND_EN BIT(4)
> +#define VID_VSYNC_3DFORMAT_LINE (0 << 2)
> +#define VID_VSYNC_3DFORMAT_FRAME (1 << 2)
> +#define VID_VSYNC_3DFORMAT_PIXEL (2 << 2)
> +#define VID_VSYNC_3DMODE_OFF 0
> +#define VID_VSYNC_3DMODE_PORTRAIT 1
> +#define VID_VSYNC_3DMODE_LANDSCAPE 2
> +
> +#define MCTL_MAIN_STS 0x24
> +#define MCTL_MAIN_STS_CTL 0x130
> +#define MCTL_MAIN_STS_CLR 0x150
> +#define MCTL_MAIN_STS_FLAG 0x170
> +#define HS_SKEWCAL_DONE BIT(11)
> +#define IF_UNTERM_PKT_ERR(x) BIT(8 + (x))
> +#define LPRX_TIMEOUT_ERR BIT(7)
> +#define HSTX_TIMEOUT_ERR BIT(6)
> +#define DATA_LANE_RDY(l) BIT(2 + (l))
> +#define CLK_LANE_RDY BIT(1)
> +#define PLL_LOCKED BIT(0)
> +
> +#define MCTL_DPHY_ERR 0x28
> +#define MCTL_DPHY_ERR_CTL1 0x148
> +#define MCTL_DPHY_ERR_CLR 0x168
> +#define MCTL_DPHY_ERR_FLAG 0x188
> +#define ERR_CONT_LP(x, l) BIT(18 + ((x) * 4) + (l))
> +#define ERR_CONTROL(l) BIT(14 + (l))
> +#define ERR_SYNESC(l) BIT(10 + (l))
> +#define ERR_ESC(l) BIT(6 + (l))
> +
> +#define MCTL_DPHY_ERR_CTL2 0x14c
> +#define ERR_CONT_LP_EDGE(x, l) BIT(12 + ((x) * 4) + (l))
> +#define ERR_CONTROL_EDGE(l) BIT(8 + (l))
> +#define ERR_SYN_ESC_EDGE(l) BIT(4 + (l))
> +#define ERR_ESC_EDGE(l) BIT(0 + (l))
> +
> +#define MCTL_LANE_STS 0x2c
> +#define PPI_C_TX_READY_HS BIT(18)
> +#define DPHY_PLL_LOCK BIT(17)
> +#define PPI_D_RX_ULPS_ESC(x) (((x) & GENMASK(15, 12)) >> 12)
> +#define LANE_STATE_START 0
> +#define LANE_STATE_IDLE 1
> +#define LANE_STATE_WRITE 2
> +#define LANE_STATE_ULPM 3
> +#define LANE_STATE_READ 4
> +#define DATA_LANE_STATE(l, val) \
> + (((val) >> (2 + 2 * (l) + ((l) ? 1 : 0))) & GENMASK((l) ? 1 : 2, 0))
> +#define CLK_LANE_STATE_HS 2
> +#define CLK_LANE_STATE(val) ((val) & GENMASK(1, 0))
> +
> +#define DSC_MODE_CTL 0x30
> +#define DSC_MODE_EN BIT(0)
> +
> +#define DSC_CMD_SEND 0x34
> +#define DSC_SEND_PPS BIT(0)
> +#define DSC_EXECUTE_QUEUE BIT(1)
> +
> +#define DSC_PPS_WRDAT 0x38
> +
> +#define DSC_MODE_STS 0x3c
> +#define DSC_PPS_DONE BIT(1)
> +#define DSC_EXEC_DONE BIT(2)
> +
> +#define CMD_MODE_CTL 0x70
> +#define IF_LP_EN(x) BIT(9 + (x))
> +#define IF_VCHAN_ID(x, c) ((c) << ((x) * 2))
> +
> +#define CMD_MODE_CTL2 0x74
> +#define TE_TIMEOUT(x) ((x) << 11)
> +#define FILL_VALUE(x) ((x) << 3)
> +#define ARB_IF_WITH_HIGHEST_PRIORITY(x) ((x) << 1)
> +#define ARB_ROUND_ROBIN_MODE BIT(0)
> +
> +#define CMD_MODE_STS 0x78
> +#define CMD_MODE_STS_CTL 0x134
> +#define CMD_MODE_STS_CLR 0x154
> +#define CMD_MODE_STS_FLAG 0x174
> +#define ERR_IF_UNDERRUN(x) BIT(4 + (x))
> +#define ERR_UNWANTED_READ BIT(3)
> +#define ERR_TE_MISS BIT(2)
> +#define ERR_NO_TE BIT(1)
> +#define CSM_RUNNING BIT(0)
> +
> +#define DIRECT_CMD_SEND 0x80
> +
> +#define DIRECT_CMD_MAIN_SETTINGS 0x84
> +#define TRIGGER_VAL(x) ((x) << 25)
> +#define CMD_LP_EN BIT(24)
> +#define CMD_SIZE(x) ((x) << 16)
> +#define CMD_VCHAN_ID(x) ((x) << 14)
> +#define CMD_DATATYPE(x) ((x) << 8)
> +#define CMD_LONG BIT(3)
> +#define WRITE_CMD 0
> +#define READ_CMD 1
> +#define TE_REQ 4
> +#define TRIGGER_REQ 5
> +#define BTA_REQ 6
> +
> +#define DIRECT_CMD_STS 0x88
> +#define DIRECT_CMD_STS_CTL 0x138
> +#define DIRECT_CMD_STS_CLR 0x158
> +#define DIRECT_CMD_STS_FLAG 0x178
> +#define RCVD_ACK_VAL(val) ((val) >> 16)
> +#define RCVD_TRIGGER_VAL(val) (((val) & GENMASK(14, 11)) >> 11)
> +#define READ_COMPLETED_WITH_ERR BIT(10)
> +#define BTA_FINISHED BIT(9)
> +#define BTA_COMPLETED BIT(8)
> +#define TE_RCVD BIT(7)
> +#define TRIGGER_RCVD BIT(6)
> +#define ACK_WITH_ERR_RCVD BIT(5)
> +#define ACK_RCVD BIT(4)
> +#define READ_COMPLETED BIT(3)
> +#define TRIGGER_COMPLETED BIT(2)
> +#define WRITE_COMPLETED BIT(1)
> +#define SENDING_CMD BIT(0)
> +
> +#define DIRECT_CMD_STOP_READ 0x8c
> +
> +#define DIRECT_CMD_WRDATA 0x90
> +
> +#define DIRECT_CMD_FIFO_RST 0x94
> +
> +#define DIRECT_CMD_RDDATA 0xa0
> +
> +#define DIRECT_CMD_RD_PROPS 0xa4
> +#define RD_DCS BIT(18)
> +#define RD_VCHAN_ID(val) (((val) >> 16) & GENMASK(1, 0))
> +#define RD_SIZE(val) ((val) & GENMASK(15, 0))
> +
> +#define DIRECT_CMD_RD_STS 0xa8
> +#define DIRECT_CMD_RD_STS_CTL 0x13c
> +#define DIRECT_CMD_RD_STS_CLR 0x15c
> +#define DIRECT_CMD_RD_STS_FLAG 0x17c
> +#define ERR_EOT_WITH_ERR BIT(8)
> +#define ERR_MISSING_EOT BIT(7)
> +#define ERR_WRONG_LENGTH BIT(6)
> +#define ERR_OVERSIZE BIT(5)
> +#define ERR_RECEIVE BIT(4)
> +#define ERR_UNDECODABLE BIT(3)
> +#define ERR_CHECKSUM BIT(2)
> +#define ERR_UNCORRECTABLE BIT(1)
> +#define ERR_FIXED BIT(0)
> +
> +#define VID_MAIN_CTL 0xb0
> +#define VID_IGNORE_MISS_VSYNC BIT(31)
> +#define VID_FIELD_SW BIT(28)
> +#define VID_INTERLACED_EN BIT(27)
> +#define RECOVERY_MODE(x) ((x) << 25)
> +#define RECOVERY_MODE_NEXT_HSYNC 0
> +#define RECOVERY_MODE_NEXT_STOP_POINT 2
> +#define RECOVERY_MODE_NEXT_VSYNC 3
> +#define REG_BLKEOL_MODE(x) ((x) << 23)
> +#define REG_BLKLINE_MODE(x) ((x) << 21)
> +#define REG_BLK_MODE_NULL_PKT 0
> +#define REG_BLK_MODE_BLANKING_PKT 1
> +#define REG_BLK_MODE_LP 2
> +#define SYNC_PULSE_HORIZONTAL BIT(20)
> +#define SYNC_PULSE_ACTIVE BIT(19)
> +#define BURST_MODE BIT(18)
> +#define VID_PIXEL_MODE_MASK GENMASK(17, 14)
> +#define VID_PIXEL_MODE_RGB565 (0 << 14)
> +#define VID_PIXEL_MODE_RGB666_PACKED (1 << 14)
> +#define VID_PIXEL_MODE_RGB666 (2 << 14)
> +#define VID_PIXEL_MODE_RGB888 (3 << 14)
> +#define VID_PIXEL_MODE_RGB101010 (4 << 14)
> +#define VID_PIXEL_MODE_RGB121212 (5 << 14)
> +#define VID_PIXEL_MODE_YUV420 (8 << 14)
> +#define VID_PIXEL_MODE_YUV422_PACKED (9 << 14)
> +#define VID_PIXEL_MODE_YUV422 (10 << 14)
> +#define VID_PIXEL_MODE_YUV422_24B (11 << 14)
> +#define VID_PIXEL_MODE_DSC_COMP (12 << 14)
> +#define VID_DATATYPE(x) ((x) << 8)
> +#define VID_VIRTCHAN_ID(iface, x) ((x) << (4 + (iface) * 2))
> +#define STOP_MODE(x) ((x) << 2)
> +#define START_MODE(x) (x)
> +
> +#define VID_VSIZE1 0xb4
> +#define VFP_LEN(x) ((x) << 12)
> +#define VBP_LEN(x) ((x) << 6)
> +#define VSA_LEN(x) (x)
> +
> +#define VID_VSIZE2 0xb8
> +#define VACT_LEN(x) (x)
> +
> +#define VID_HSIZE1 0xc0
> +#define HBP_LEN(x) ((x) << 16)
> +#define HSA_LEN(x) (x)
> +
> +#define VID_HSIZE2 0xc4
> +#define HFP_LEN(x) ((x) << 16)
> +#define HACT_LEN(x) (x)
> +
> +#define VID_BLKSIZE1 0xcc
> +#define BLK_EOL_PKT_LEN(x) ((x) << 15)
> +#define BLK_LINE_EVENT_PKT_LEN(x) (x)
> +
> +#define VID_BLKSIZE2 0xd0
> +#define BLK_LINE_PULSE_PKT_LEN(x) (x)
> +
> +#define VID_PKT_TIME 0xd8
> +#define BLK_EOL_DURATION(x) (x)
> +
> +#define VID_DPHY_TIME 0xdc
> +#define REG_WAKEUP_TIME(x) ((x) << 17)
> +#define REG_LINE_DURATION(x) (x)
> +
> +#define VID_ERR_COLOR1 0xe0
> +#define COL_GREEN(x) ((x) << 12)
> +#define COL_RED(x) (x)
> +
> +#define VID_ERR_COLOR2 0xe4
> +#define PAD_VAL(x) ((x) << 12)
> +#define COL_BLUE(x) (x)
> +
> +#define VID_VPOS 0xe8
> +#define LINE_VAL(val) (((val) & GENMASK(14, 2)) >> 2)
> +#define LINE_POS(val) ((val) & GENMASK(1, 0))
> +
> +#define VID_HPOS 0xec
> +#define HORIZ_VAL(val) (((val) & GENMASK(17, 3)) >> 3)
> +#define HORIZ_POS(val) ((val) & GENMASK(2, 0))
> +
> +#define VID_MODE_STS 0xf0
> +#define VID_MODE_STS_CTL 0x140
> +#define VID_MODE_STS_CLR 0x160
> +#define VID_MODE_STS_FLAG 0x180
> +#define VSG_RECOVERY BIT(10)
> +#define ERR_VRS_WRONG_LEN BIT(9)
> +#define ERR_LONG_READ BIT(8)
> +#define ERR_LINE_WRITE BIT(7)
> +#define ERR_BURST_WRITE BIT(6)
> +#define ERR_SMALL_HEIGHT BIT(5)
> +#define ERR_SMALL_LEN BIT(4)
> +#define ERR_MISSING_VSYNC BIT(3)
> +#define ERR_MISSING_HSYNC BIT(2)
> +#define ERR_MISSING_DATA BIT(1)
> +#define VSG_RUNNING BIT(0)
> +
> +#define VID_VCA_SETTING1 0xf4
> +#define BURST_LP BIT(16)
> +#define MAX_BURST_LIMIT(x) (x)
> +
> +#define VID_VCA_SETTING2 0xf8
> +#define MAX_LINE_LIMIT(x) ((x) << 16)
> +#define EXACT_BURST_LIMIT(x) (x)
> +
> +#define TVG_CTL 0xfc
> +#define TVG_STRIPE_SIZE(x) ((x) << 5)
> +#define TVG_MODE_MASK GENMASK(4, 3)
> +#define TVG_MODE_SINGLE_COLOR (0 << 3)
> +#define TVG_MODE_VSTRIPES (2 << 3)
> +#define TVG_MODE_HSTRIPES (3 << 3)
> +#define TVG_STOPMODE_MASK GENMASK(2, 1)
> +#define TVG_STOPMODE_EOF (0 << 1)
> +#define TVG_STOPMODE_EOL (1 << 1)
> +#define TVG_STOPMODE_NOW (2 << 1)
> +#define TVG_RUN BIT(0)
> +
> +#define TVG_IMG_SIZE 0x100
> +#define TVG_NBLINES(x) ((x) << 16)
> +#define TVG_LINE_SIZE(x) (x)
> +
> +#define TVG_COLOR1 0x104
> +#define TVG_COL1_GREEN(x) ((x) << 12)
> +#define TVG_COL1_RED(x) (x)
> +
> +#define TVG_COLOR1_BIS 0x108
> +#define TVG_COL1_BLUE(x) (x)
> +
> +#define TVG_COLOR2 0x10c
> +#define TVG_COL2_GREEN(x) ((x) << 12)
> +#define TVG_COL2_RED(x) (x)
> +
> +#define TVG_COLOR2_BIS 0x110
> +#define TVG_COL2_BLUE(x) (x)
> +
> +#define TVG_STS 0x114
> +#define TVG_STS_CTL 0x144
> +#define TVG_STS_CLR 0x164
> +#define TVG_STS_FLAG 0x184
> +#define TVG_STS_RUNNING BIT(0)
> +
> +#define STS_CTL_EDGE(e) ((e) << 16)
> +
> +#define DPHY_LANES_MAP 0x198
> +#define DAT_REMAP_CFG(b, l) ((l) << ((b) * 8))
> +
> +#define DPI_IRQ_EN 0x1a0
> +#define DPI_IRQ_CLR 0x1a4
> +#define DPI_IRQ_STS 0x1a8
> +#define PIXEL_BUF_OVERFLOW BIT(0)
> +
> +#define DPI_CFG 0x1ac
> +#define DPI_CFG_FIFO_DEPTH(x) ((x) >> 16)
> +#define DPI_CFG_FIFO_LEVEL(x) ((x) & GENMASK(15, 0))
> +
> +#define TEST_GENERIC 0x1f0
> +#define TEST_STATUS(x) ((x) >> 16)
> +#define TEST_CTRL(x) (x)
> +
> +#define ID_REG 0x1fc
> +#define REV_VENDOR_ID(x) (((x) & GENMASK(31, 20)) >> 20)
> +#define REV_PRODUCT_ID(x) (((x) & GENMASK(19, 12)) >> 12)
> +#define REV_HW(x) (((x) & GENMASK(11, 8)) >> 8)
> +#define REV_MAJOR(x) (((x) & GENMASK(7, 4)) >> 4)
> +#define REV_MINOR(x) ((x) & GENMASK(3, 0))
> +
> +#define DSI_OUTPUT_PORT 0
> +#define DSI_INPUT_PORT(inputid) (1 + (inputid))
> +
> +#define DSI_HBP_FRAME_OVERHEAD 12
> +#define DSI_HSA_FRAME_OVERHEAD 14
> +#define DSI_HFP_FRAME_OVERHEAD 6
> +#define DSI_HSS_VSS_VSE_FRAME_OVERHEAD 4
> +#define DSI_BLANKING_FRAME_OVERHEAD 6
> +#define DSI_NULL_FRAME_OVERHEAD 6
> +#define DSI_EOT_PKT_SIZE 4
> +
> +#define REG_WAKEUP_TIME_NS 800
> +#define DPHY_PLL_RATE_HZ 108000000
> +
> +/* DPHY registers */
> +#define DPHY_PMA_CMN(reg) (reg)
> +#define DPHY_PMA_LCLK(reg) (0x100 + (reg))
> +#define DPHY_PMA_LDATA(lane, reg) (0x200 + ((lane) * 0x100) + (reg))
> +#define DPHY_PMA_RCLK(reg) (0x600 + (reg))
> +#define DPHY_PMA_RDATA(lane, reg) (0x700 + ((lane) * 0x100) + (reg))
> +#define DPHY_PCS(reg) (0xb00 + (reg))
> +
> +#define DPHY_CMN_SSM DPHY_PMA_CMN(0x20)
> +#define DPHY_CMN_SSM_EN BIT(0)
> +#define DPHY_CMN_TX_MODE_EN BIT(9)
> +
> +#define DPHY_CMN_PWM DPHY_PMA_CMN(0x40)
> +#define DPHY_CMN_PWM_DIV(x) ((x) << 20)
> +#define DPHY_CMN_PWM_LOW(x) ((x) << 10)
> +#define DPHY_CMN_PWM_HIGH(x) (x)
> +
> +#define DPHY_CMN_FBDIV DPHY_PMA_CMN(0x4c)
> +#define DPHY_CMN_FBDIV_VAL(low, high) (((high) << 11) | ((low) << 22))
> +#define DPHY_CMN_FBDIV_FROM_REG (BIT(10) | BIT(21))
> +
> +#define DPHY_CMN_OPIPDIV DPHY_PMA_CMN(0x50)
> +#define DPHY_CMN_IPDIV_FROM_REG BIT(0)
> +#define DPHY_CMN_IPDIV(x) ((x) << 1)
> +#define DPHY_CMN_OPDIV_FROM_REG BIT(6)
> +#define DPHY_CMN_OPDIV(x) ((x) << 7)
> +
> +#define DPHY_PSM_CFG DPHY_PCS(0x4)
> +#define DPHY_PSM_CFG_FROM_REG BIT(0)
> +#define DPHY_PSM_CLK_DIV(x) ((x) << 1)
> +
> +struct cdns_dsi_output {
> + struct mipi_dsi_device *dev;
> + struct drm_panel *panel;
> + struct drm_bridge *bridge;
> +};
> +
> +enum cdns_dsi_input_id {
> + CDNS_SDI_INPUT,
> + CDNS_DPI_INPUT,
> + CDNS_DSC_INPUT,
> +};
> +
> +struct cdns_dphy_cfg {
> + u8 pll_ipdiv;
> + u8 pll_opdiv;
> + u16 pll_fbdiv;
> + unsigned long lane_bps;
> + unsigned int nlanes;
> +};
> +
> +struct cdns_dsi_cfg {
> + unsigned int hfp;
> + unsigned int hsa;
> + unsigned int hbp;
> + unsigned int hact;
> + unsigned int htotal;
> +};
> +
> +struct cdns_dphy;
> +
> +enum cdns_dphy_clk_lane_cfg {
> + DPHY_CLK_CFG_LEFT_DRIVES_ALL = 0,
> + DPHY_CLK_CFG_LEFT_DRIVES_RIGHT = 1,
> + DPHY_CLK_CFG_LEFT_DRIVES_LEFT = 2,
> + DPHY_CLK_CFG_RIGHT_DRIVES_ALL = 3,
> +};
> +
> +struct cdns_dphy_ops {
> + int (*probe)(struct cdns_dphy *dphy);
> + void (*remove)(struct cdns_dphy *dphy);
> + void (*set_psm_div)(struct cdns_dphy *dphy, u8 div);
> + void (*set_clk_lane_cfg)(struct cdns_dphy *dphy,
> + enum cdns_dphy_clk_lane_cfg cfg);
> + void (*set_pll_cfg)(struct cdns_dphy *dphy,
> + const struct cdns_dphy_cfg *cfg);
> + unsigned long (*get_wakeup_time_ns)(struct cdns_dphy *dphy);
> +};
> +
> +struct cdns_dphy {
> + struct cdns_dphy_cfg cfg;
> + void __iomem *regs;
> + struct clk *psm_clk;
> + struct clk *pll_ref_clk;
> + const struct cdns_dphy_ops *ops;
> +};
> +
> +struct cdns_dsi_input {
> + enum cdns_dsi_input_id id;
> + struct drm_bridge bridge;
> +};
> +
> +struct cdns_dsi {
> + struct mipi_dsi_host base;
> + void __iomem *regs;
> + struct cdns_dsi_input input;
> + struct cdns_dsi_output output;
> + unsigned int direct_cmd_fifo_depth;
> + unsigned int rx_fifo_depth;
> + struct completion direct_cmd_comp;
> + struct clk *dsi_p_clk;
> + struct reset_control *dsi_p_rst;
> + struct clk *dsi_sys_clk;
> + bool link_initialized;
> + struct cdns_dphy *dphy;
> +};
> +
> +static inline struct cdns_dsi *input_to_dsi(struct cdns_dsi_input *input)
> +{
> + return container_of(input, struct cdns_dsi, input);
> +}
> +
> +static inline struct cdns_dsi *to_cdns_dsi(struct mipi_dsi_host *host)
> +{
> + return container_of(host, struct cdns_dsi, base);
> +}
> +
> +static inline struct cdns_dsi_input *
> +bridge_to_cdns_dsi_input(struct drm_bridge *bridge)
> +{
> + return container_of(bridge, struct cdns_dsi_input, bridge);
> +}
> +
> +static int cdns_dsi_get_dphy_pll_cfg(struct cdns_dphy *dphy,
> + struct cdns_dphy_cfg *cfg,
> + unsigned int dpi_htotal,
> + unsigned int dpi_bpp,
> + unsigned int dpi_hz,
> + unsigned int dsi_htotal,
> + unsigned int dsi_nlanes,
> + unsigned int *dsi_hfp_ext)
> +{
> + u64 dlane_bps, dlane_bps_max, fbdiv, fbdiv_max, adj_dsi_htotal;
> + unsigned long pll_ref_hz = clk_get_rate(dphy->pll_ref_clk);
> +
> + memset(cfg, 0, sizeof(*cfg));
> +
> + cfg->nlanes = dsi_nlanes;
> +
> + if (pll_ref_hz < 9600000 || pll_ref_hz >= 150000000)
> + return -EINVAL;
> + else if (pll_ref_hz < 19200000)
> + cfg->pll_ipdiv = 1;
> + else if (pll_ref_hz < 38400000)
> + cfg->pll_ipdiv = 2;
> + else if (pll_ref_hz < 76800000)
> + cfg->pll_ipdiv = 4;
> + else
> + cfg->pll_ipdiv = 8;
> +
> + /*
> + * Make sure DSI htotal is aligned on a lane boundary when calculating
> + * the expected data rate. This is done by extending HFP in case of
> + * misalignment.
> + */
> + adj_dsi_htotal = dsi_htotal;
> + if (dsi_htotal % dsi_nlanes)
> + adj_dsi_htotal += dsi_nlanes - (dsi_htotal % dsi_nlanes);
> +
> + dlane_bps = (u64)dpi_hz * adj_dsi_htotal;
> +
> + /* data rate in bytes/sec is not an integer, refuse the mode. */
> + if (do_div(dlane_bps, dsi_nlanes * dpi_htotal))
> + return -EINVAL;
> +
> + /* data rate was in bytes/sec, convert to bits/sec. */
> + dlane_bps *= 8;
> +
> + if (dlane_bps > 2500000000UL || dlane_bps < 160000000UL)
> + return -EINVAL;
> + else if (dlane_bps >= 1250000000)
> + cfg->pll_opdiv = 1;
> + else if (dlane_bps >= 630000000)
> + cfg->pll_opdiv = 2;
> + else if (dlane_bps >= 320000000)
> + cfg->pll_opdiv = 4;
> + else if (dlane_bps >= 160000000)
> + cfg->pll_opdiv = 8;
> +
> + /*
> + * Allow a deviation of 0.2% on the per-lane data rate to try to
> + * recover a potential mismatch between DPI and PPI clks.
> + */
> + dlane_bps_max = dlane_bps + (dlane_bps / 500);
kbuild reported an error for 32 bit archs. I'm guessing it's because of
this divide above?
> +
> + fbdiv_max = DIV_ROUND_DOWN_ULL((dlane_bps + (dlane_bps / 500)) * 2 *
You could use dlane_bps_max here instead.
Otherwise,
Reviewed-by: Archit Taneja <architt at codeaurora.org>
Thanks,
Archit
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