[PATCH v3 2/7] drm/bridge: ti-sn65dsi86: Fixup register names
spanda at codeaurora.org
spanda at codeaurora.org
Tue Aug 14 10:50:21 UTC 2018
On 2018-08-14 03:00, Sean Paul wrote:
> From: Sean Paul <seanpaul at chromium.org>
>
> Order registers by offset and rename bits & masks to match the
> datasheet. This makes the driver a bit easier to grok and
> cross-reference with the datasheet.
>
> Changes in v3:
> - Added to the set
>
> Cc: Sandeep Panda <spanda at codeaurora.org>
> Signed-off-by: Sean Paul <seanpaul at chromium.org>
> ---
> drivers/gpu/drm/bridge/ti-sn65dsi86.c | 92 +++++++++++++--------------
> 1 file changed, 45 insertions(+), 47 deletions(-)
>
> diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c
> b/drivers/gpu/drm/bridge/ti-sn65dsi86.c
> index 1b6e8b72be584..587d4e4f5674c 100644
> --- a/drivers/gpu/drm/bridge/ti-sn65dsi86.c
> +++ b/drivers/gpu/drm/bridge/ti-sn65dsi86.c
> @@ -18,36 +18,51 @@
> #include <linux/regmap.h>
> #include <linux/regulator/consumer.h>
>
> -/* Link Training specific registers */
> #define SN_DEVICE_REV_REG 0x08
> -#define SN_HPD_DISABLE_REG 0x5C
> #define SN_DPPLL_SRC_REG 0x0A
> +#define DPPLL_CLK_SRC_DSICLK BIT(0)
> +#define REFCLK_FREQ_MASK GENMASK(3, 1)
> +#define REFCLK_FREQ(x) ((x) << 1)
> +#define DPPLL_SRC_DP_PLL_LOCK BIT(7)
> +#define SN_PLL_ENABLE_REG 0x0D
> #define SN_DSI_LANES_REG 0x10
> +#define CHA_DSI_LANES_MASK GENMASK(4, 3)
> +#define CHA_DSI_LANES(x) ((x) << 3)
> #define SN_DSIA_CLK_FREQ_REG 0x12
> -#define SN_ENH_FRAME_REG 0x5A
> -#define SN_SSC_CONFIG_REG 0x93
> -#define SN_DATARATE_CONFIG_REG 0x94
> -#define SN_PLL_ENABLE_REG 0x0D
> -#define SN_SCRAMBLE_CONFIG_REG 0x95
> -#define SN_AUX_WDATA0_REG 0x64
> -#define SN_AUX_ADDR_19_16_REG 0x74
> -#define SN_AUX_ADDR_15_8_REG 0x75
> -#define SN_AUX_ADDR_7_0_REG 0x76
> -#define SN_AUX_LENGTH_REG 0x77
> -#define SN_AUX_CMD_REG 0x78
> -#define SN_ML_TX_MODE_REG 0x96
> -/* video config specific registers */
> #define SN_CHA_ACTIVE_LINE_LENGTH_LOW_REG 0x20
> #define SN_CHA_VERTICAL_DISPLAY_SIZE_LOW_REG 0x24
> #define SN_CHA_HSYNC_PULSE_WIDTH_LOW_REG 0x2C
> #define SN_CHA_HSYNC_PULSE_WIDTH_HIGH_REG 0x2D
> +#define CHA_HSYNC_POLARITY BIT(7)
> #define SN_CHA_VSYNC_PULSE_WIDTH_LOW_REG 0x30
> #define SN_CHA_VSYNC_PULSE_WIDTH_HIGH_REG 0x31
> +#define CHA_VSYNC_POLARITY BIT(7)
> #define SN_CHA_HORIZONTAL_BACK_PORCH_REG 0x34
> #define SN_CHA_VERTICAL_BACK_PORCH_REG 0x36
> #define SN_CHA_HORIZONTAL_FRONT_PORCH_REG 0x38
> #define SN_CHA_VERTICAL_FRONT_PORCH_REG 0x3A
> +#define SN_ENH_FRAME_REG 0x5A
> +#define VSTREAM_ENABLE BIT(3)
> #define SN_DATA_FORMAT_REG 0x5B
> +#define SN_HPD_DISABLE_REG 0x5C
> +#define HPD_DISABLE BIT(0)
> +#define SN_AUX_WDATA0_REG 0x64
> +#define SN_AUX_ADDR_19_16_REG 0x74
> +#define SN_AUX_ADDR_15_8_REG 0x75
> +#define SN_AUX_ADDR_7_0_REG 0x76
> +#define SN_AUX_LENGTH_REG 0x77
> +#define SN_AUX_CMD_REG 0x78
> +#define AUX_CMD_SEND BIT(1)
> +#define AUX_CMD_REQ(x) ((x) << 4)
> +#define SN_SSC_CONFIG_REG 0x93
> +#define DP_NUM_LANES_MASK GENMASK(5, 4)
> +#define DP_NUM_LANES(x) ((x) << 4)
> +#define SN_DATARATE_CONFIG_REG 0x94
> +#define DP_DATARATE_MASK GENMASK(7, 5)
> +#define DP_DATARATE(x) ((x) << 5)
> +#define SN_ML_TX_MODE_REG 0x96
> +#define ML_TX_MAIN_LINK_OFF 0
> +#define ML_TX_NORMAL_MODE BIT(0)
>
> #define MIN_DSI_CLK_FREQ_MHZ 40
>
> @@ -55,22 +70,6 @@
> #define DP_CLK_FUDGE_NUM 10
> #define DP_CLK_FUDGE_DEN 8
>
> -#define DPPLL_CLK_SRC_REFCLK 0
> -#define DPPLL_CLK_SRC_DSICLK 1
> -
> -#define SN_REFCLK_FREQ_OFFSET 1
> -#define SN_DSIA_LANE_OFFSET 3
> -#define SN_DP_LANE_OFFSET 4
> -#define SN_DP_DATA_RATE_OFFSET 5
> -#define SN_SYNC_POLARITY_OFFSET 7
> -
> -#define SN_ENABLE_VID_STREAM_BIT BIT(3)
> -#define SN_REFCLK_FREQ_BITS GENMASK(3, 1)
> -#define SN_DSIA_NUM_LANES_BITS GENMASK(4, 3)
> -#define SN_DP_NUM_LANES_BITS GENMASK(5, 4)
> -#define SN_DP_DATA_RATE_BITS GENMASK(7, 5)
> -#define SN_HPD_DISABLE_BIT BIT(0)
> -
> #define SN_REGULATOR_SUPPLY_NUM 4
>
> struct ti_sn_bridge {
> @@ -299,8 +298,7 @@ static void ti_sn_bridge_disable(struct drm_bridge
> *bridge)
> drm_panel_disable(pdata->panel);
>
> /* disable video stream */
> - regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG,
> - SN_ENABLE_VID_STREAM_BIT, 0);
> + regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, VSTREAM_ENABLE,
> 0);
> /* semi auto link training mode OFF */
> regmap_write(pdata->regmap, SN_ML_TX_MODE_REG, 0);
> /* disable DP PLL */
> @@ -363,8 +361,8 @@ static void ti_sn_bridge_set_refclk_freq(struct
> ti_sn_bridge *pdata)
> if (refclk_lut[i] == refclk_rate)
> break;
>
> - regmap_update_bits(pdata->regmap, SN_DPPLL_SRC_REG,
> - SN_REFCLK_FREQ_BITS, i << SN_REFCLK_FREQ_OFFSET);
> + regmap_update_bits(pdata->regmap, SN_DPPLL_SRC_REG, REFCLK_FREQ_MASK,
> + REFCLK_FREQ(i));
> }
>
> /**
> @@ -401,7 +399,7 @@ static void ti_sn_bridge_set_dsi_dp_rate(struct
> ti_sn_bridge *pdata)
> break;
>
> regmap_update_bits(pdata->regmap, SN_DATARATE_CONFIG_REG,
> - SN_DP_DATA_RATE_BITS, i << SN_DP_DATA_RATE_OFFSET);
> + DP_DATARATE_MASK, DP_DATARATE(i));
> }
>
> static void ti_sn_bridge_set_video_timings(struct ti_sn_bridge *pdata)
> @@ -411,9 +409,9 @@ static void ti_sn_bridge_set_video_timings(struct
> ti_sn_bridge *pdata)
> u8 hsync_polarity = 0, vsync_polarity = 0;
>
> if (mode->flags & DRM_MODE_FLAG_PHSYNC)
> - hsync_polarity = BIT(SN_SYNC_POLARITY_OFFSET);
> + hsync_polarity = CHA_HSYNC_POLARITY;
> if (mode->flags & DRM_MODE_FLAG_PVSYNC)
> - vsync_polarity = BIT(SN_SYNC_POLARITY_OFFSET);
> + vsync_polarity = CHA_VSYNC_POLARITY;
>
> ti_sn_bridge_write_u16(pdata, SN_CHA_ACTIVE_LINE_LENGTH_LOW_REG,
> mode->hdisplay);
> @@ -451,14 +449,14 @@ static void ti_sn_bridge_enable(struct drm_bridge
> *bridge)
> drm_panel_prepare(pdata->panel);
>
> /* DSI_A lane config */
> - val = (4 - pdata->dsi->lanes) << SN_DSIA_LANE_OFFSET;
> + val = CHA_DSI_LANES(4 - pdata->dsi->lanes);
> regmap_update_bits(pdata->regmap, SN_DSI_LANES_REG,
> - SN_DSIA_NUM_LANES_BITS, val);
> + CHA_DSI_LANES_MASK, val);
>
> /* DP lane config */
> - val = (pdata->dsi->lanes - 1) << SN_DP_LANE_OFFSET;
> - regmap_update_bits(pdata->regmap, SN_SSC_CONFIG_REG,
> - SN_DP_NUM_LANES_BITS, val);
> + val = DP_NUM_LANES(pdata->dsi->lanes - 1);
> + regmap_update_bits(pdata->regmap, SN_SSC_CONFIG_REG,
> DP_NUM_LANES_MASK,
> + val);
>
> /* set dsi/dp clk frequency value */
> ti_sn_bridge_set_dsi_dp_rate(pdata);
> @@ -489,8 +487,8 @@ static void ti_sn_bridge_enable(struct drm_bridge
> *bridge)
> ti_sn_bridge_set_video_timings(pdata);
>
> /* enable video stream */
> - regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG,
> - SN_ENABLE_VID_STREAM_BIT, SN_ENABLE_VID_STREAM_BIT);
> + regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, VSTREAM_ENABLE,
> + VSTREAM_ENABLE);
>
> drm_panel_enable(pdata->panel);
> }
> @@ -505,8 +503,8 @@ static void ti_sn_bridge_pre_enable(struct
> drm_bridge *bridge)
> ti_sn_bridge_set_refclk_freq(pdata);
>
> /* in case drm_panel is connected then HPD is not supported */
> - regmap_update_bits(pdata->regmap, SN_HPD_DISABLE_REG,
> - SN_HPD_DISABLE_BIT, SN_HPD_DISABLE_BIT);
> + regmap_update_bits(pdata->regmap, SN_HPD_DISABLE_REG, HPD_DISABLE,
> + HPD_DISABLE);
> }
>
> static void ti_sn_bridge_post_disable(struct drm_bridge *bridge)
Reviewed-by: Sandeep Panda <spanda at codeaurora.org>
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