[PATCH v3 3/8] drm/msm/dsi: 28nm PHY: Get ref clock from the DT

[Stephen Boyd]

Quoting Matthias Kaehlcke (2018-11-30 16:52:49)
> diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c
> index 26e3a01a99c2b..4a84c69ca0b2b 100644
> --- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c
> +++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c
> @@ -81,6 +81,7 @@ struct dsi_pll_28nm {
>         struct platform_device *pdev;
>         void __iomem *mmio;
>  
> +       const char *vco_ref_clk_name;
>         int vco_delay;
>  
>         /* private clocks: */
> @@ -265,7 +268,8 @@ static unsigned long dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw,
>         void __iomem *base = pll_28nm->mmio;
>         u32 sdm0, doubler, sdm_byp_div;
>         u32 sdm_dc_off, sdm_freq_seed, sdm2, sdm3;
> -       u32 ref_clk = VCO_REF_CLK_RATE;
> +       u32 ref_clk = parent_rate ?
> +               parent_rate : VCO_REF_CLK_DEFAULT_RATE;

Same comments apply here.

>         unsigned long vco_rate;
>  
>         VERB("parent_rate=%lu", parent_rate);