[PATCH v2 07/16] drm: rcar-du: Use LVDS PLL clock as dot clock when possible

[Kuninori Morimoto]

Hi Laurent

> > > +	didsr = DIDSR_CODE;
> > > +	for (i = 0; i < num_crtcs; ++i, ++rcrtc) {
> > > +		if (rcdu->info->lvds_clk_mask & BIT(rcrtc->index))
> > > +			didsr |= DIDSR_LCDS_LVDS0(i)
> > > +			      |  DIDSR_PDCS_CLK(i, 0);
> > > +		else
> > > +			didsr |= DIDSR_LCDS_DCLKIN(i)
> > > +			      |  DIDSR_PDCS_CLK(i, 0);
> > > +	}
> > 
> > Here, this is for DU pin settings, and fixed for
> > 
> > 	DU_DOTCLKIN0 -> DU0
> > 	DU_DOTCLKIN1 -> DU1
> > 
> > But on E3 (Ebisu) board, it has only DU_DOTCLKIN0.
> > We might use like this
> > 
> > 	DU_DOTCLKIN0 -> DU0
> > 	DU_DOTCLKIN0 -> DU1
> > 
> > It is possible to adjust to this situation ?
> > DIDSR :: PDCSn allows only 0
> 
> I think this would make sense. I'm not sure how to implement that, but I'll 
> give it a try. What is the priority ?

Normal priority is very OK, so far.
Thank you

Best regards
---
Kuninori Morimoto