[Intel-gfx] [PATCH 1/5] drm/dp/mst: Configure no_stop_bit correctly for remote i2c xfers

[Dhinakaran Pandiyan]

On Mon, 2018-12-10 at 18:39 +0200, Ville Syrjälä wrote:
> On Fri, Dec 07, 2018 at 12:45:25PM -0800, Dhinakaran Pandiyan wrote:
> > On Fri, 2018-09-28 at 21:03 +0300, Ville Syrjala wrote:
> > > From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> > > 
> > > We aren't supposed to force a stop+start between every i2c msg
> > > when performing multi message transfers. This should eg. cause
> > > the DDC segment address to be reset back to 0 between writing
> > > the segment address and reading the actual EDID extension block.
> > > 
> > > To quote the E-DDC spec:
> > > "... this standard requires that the segment pointer be
> > >  reset to 00h when a NO ACK or a STOP condition is received."
> > 
> > Related question, do you know why the segment and ddc addresses are
> > defined as 0x30 and 0x50? The E-DDC spec says they should be at
> > 0x60
> > and 0xA0/0xA1.
> 
> The spec uses 'slave_address << 1 | r/w'.
Got it, thanks.

-DK