[PATCH v4 4/8] drm/msm/dsi: 14nm PHY: Get ref clock from the DT

[Stephen Boyd]

Quoting Matthias Kaehlcke (2018-12-04 14:42:30)
> diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c
> index 71fe60e5f01f1..032bf3e8614bd 100644
> --- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c
> +++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c
> @@ -40,7 +40,6 @@
>  
>  #define NUM_PROVIDED_CLKS              2
>  
> -#define VCO_REF_CLK_RATE               19200000
>  #define VCO_MIN_RATE                   1300000000UL
>  #define VCO_MAX_RATE                   2600000000UL
>  
> @@ -139,6 +138,7 @@ struct dsi_pll_14nm {
>         /* protects REG_DSI_14nm_PHY_CMN_CLK_CFG0 register */
>         spinlock_t postdiv_lock;
>  
> +       struct clk *vco_ref_clk;

Is there any need to keep it in the struct? Or just get the clk, find
the rate, and then put the clk and call pll_14nm_postdiv_register()?

>         u64 vco_current_rate;
>         u64 vco_ref_clk_rate;
>