[PATCH v6 1/2] dt-bindings: drm/msm/a6xx: Document GMU and update GPU bindings

[Doug Anderson]

Hi,

On Wed, Dec 12, 2018 at 1:18 PM Jordan Crouse <jcrouse at codeaurora.org> wrote:
> diff --git a/Documentation/devicetree/bindings/display/msm/gpu.txt b/Documentation/devicetree/bindings/display/msm/gpu.txt
> index 43fac0fe09bb..8d9415180c22 100644
> --- a/Documentation/devicetree/bindings/display/msm/gpu.txt
> +++ b/Documentation/devicetree/bindings/display/msm/gpu.txt
> @@ -8,14 +8,21 @@ Required properties:
>    with the chip-id.
>  - reg: Physical base address and length of the controller's registers.
>  - interrupts: The interrupt signal from the gpu.
> -- clocks: device clocks
> +- interrupt-names: List of names for the interrupt signals. The following can be
> +  provided:
> +  * "kgsl_3d0_irq"
> +- clocks: device clocks (if applicable)
>    See ../clocks/clock-bindings.txt for details.
> -- clock-names: the following clocks are required:
> +- clock-names: the following clocks can be provided:
>    * "core"
>    * "iface"
>    * "mem_iface"
> +- iommus: optional phandle to an adreno iommu instance
> +- operating-points-v2: optional phandle to the OPP operating points
> +- qcom,gmu: For a6xx and newer targets a phandle to the GMU device that will
> +  control the power for the GPU

Seems fine to me.  If you happen to spin it again for some other
reason it might be nice to be more explicit about exactly when clocks
are required and when they aren't.   IIUC they are always required on
systems without a GMU and they are never present on systems with a
GMU.  ...but I wouldn't spin it just for that.

Reviewed-by: Douglas Anderson <dianders at chromium.org>