[PATCH 0/1] drm/i915: Enable fastset by default, except on initial modeset

[Rodrigo Vivi]

On Tue, Dec 18, 2018 at 05:07:34PM +0100, Hans de Goede wrote:
> Hi,
> 
> On 17-12-18 19:43, Rodrigo Vivi wrote:
> > On Mon, Dec 17, 2018 at 03:23:14PM +0100, Hans de Goede wrote:
> > > Hi All,
> > > 
> > > As discussed a while ago, I would like to see us enable fastboot by
> > > default, starting with Skylake / GEN9 and newer hardware, so that we can
> > > avoid an unnecessary modeset at boot and move to a truely flickerfree boot.
> > > 
> > > During our previous discussion about this Maarten mentioned that a first
> > > step would be to get this patch from him upstream. So I'm hereby
> > > resubmitting it, with a small fix. Hopefully the CI will like it better
> > > this time (if not we will need to investigate) and once this passes CI
> > > I hope this can be reviewed quickly and we can get this upstream.
> > 
> > I honestly believe the first step is to make sure FBC, PSR, DRRS features > gets enabled somehow with fastboot.
> 
> That is a good point, FBC will already be enabled on a fastboot as
> intel_update_crtc does:
> 
>         if (new_plane_state)
>                 intel_fbc_enable(intel_crtc, pipe_config, new_plane_state);

oh cool!

> 
> Independent of need_modeset() returning true.
> 
> PSR indeed stays off, even if i915.enable_psr=1 is passed on the kernel
> commandline. I've just completed writing a patch-set (2 patches) fixing
> this. I will submit these upstream soon.

cool, thanks!

> 
> DRRS seems to be the same as PSR (I don't have hw to test) I will also
> submit 2 patches building on top of the previous 2 which should fix this,
> we already allow runtime enabling/disabling through i915_drrs_ctl in
> debugfs, so these 2 patches should be fine.

yeap, I think so

> 
> 
> > Maybe DSC as well?!
> 
> DSC? :

VESA's Display Stream Compression

> 
> [hans at shalem linux]$ grep -r dsc  drivers/gpu/drm/i915
> [hans at shalem linux]$

*** intel_ddi.c:
intel_ddi_pre_enable_dp[3211]  intel_dsc_enable(encoder, crtc_state);

*** intel_vdsc.c:
intel_dsc_enable[1018]         void intel_dsc_enable(struct intel_encoder *encoder,

> 
> > Right now as I can remember FBC, PSR, and DRRS will get disabled if fastboot
> > is used because we just enable those when enabling the pipe.
> 
> You're right for PSR and DRRS, as Maarten just found out FBC has the
> opposite problem, we don't turn it off on a fastset when it was enabled and we
> decide it should no longer be enabled.
> 
> Regards,
> 
> Hans
> 

Thanks a lot for this work,
Rodrigo.