[PATCH] drm/doc: Move bridge link target to the right place
kbuild test robot
lkp at intel.com
Thu Dec 20 19:23:31 UTC 2018
Hi Daniel,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on v4.20-rc7 next-20181220]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Daniel-Vetter/drm-doc-Move-bridge-link-target-to-the-right-place/20181221-021521
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-defconfig (attached as .config)
compiler: gcc-7 (Debian 7.3.0-1) 7.3.0
reproduce:
# save the attached .config to linux build tree
make ARCH=i386
All errors (new ones prefixed by >>):
In file included from drivers/gpu/drm/i915/i915_trace.h:11:0,
from drivers/gpu/drm/i915/i915_drv.h:2563,
from drivers/gpu/drm/i915/i915_gem_execbuffer.c:38:
>> drivers/gpu/drm/i915/intel_drv.h:382:1: error: version control conflict marker in file
<<<<<<< HEAD
^~~~~~~
>> drivers/gpu/drm/i915/intel_drv.h:414:9: error: invalid suffix "f9e07e71945..." on integer constant
>>>>>>> 4f9e07e71945... drm/doc: Move bridge link target to the right place
^~~~~~~~~~~~~~~
vim +382 drivers/gpu/drm/i915/intel_drv.h
309
310 /*
311 * This structure serves as a translation layer between the generic HDCP code
312 * and the bus-specific code. What that means is that HDCP over HDMI differs
313 * from HDCP over DP, so to account for these differences, we need to
314 * communicate with the receiver through this shim.
315 *
316 * For completeness, the 2 buses differ in the following ways:
317 * - DP AUX vs. DDC
318 * HDCP registers on the receiver are set via DP AUX for DP, and
319 * they are set via DDC for HDMI.
320 * - Receiver register offsets
321 * The offsets of the registers are different for DP vs. HDMI
322 * - Receiver register masks/offsets
323 * For instance, the ready bit for the KSV fifo is in a different
324 * place on DP vs HDMI
325 * - Receiver register names
326 * Seriously. In the DP spec, the 16-bit register containing
327 * downstream information is called BINFO, on HDMI it's called
328 * BSTATUS. To confuse matters further, DP has a BSTATUS register
329 * with a completely different definition.
330 * - KSV FIFO
331 * On HDMI, the ksv fifo is read all at once, whereas on DP it must
332 * be read 3 keys at a time
333 * - Aksv output
334 * Since Aksv is hidden in hardware, there's different procedures
335 * to send it over DP AUX vs DDC
336 */
337 struct intel_hdcp_shim {
338 /* Outputs the transmitter's An and Aksv values to the receiver. */
339 int (*write_an_aksv)(struct intel_digital_port *intel_dig_port, u8 *an);
340
341 /* Reads the receiver's key selection vector */
342 int (*read_bksv)(struct intel_digital_port *intel_dig_port, u8 *bksv);
343
344 /*
345 * Reads BINFO from DP receivers and BSTATUS from HDMI receivers. The
346 * definitions are the same in the respective specs, but the names are
347 * different. Call it BSTATUS since that's the name the HDMI spec
348 * uses and it was there first.
349 */
350 int (*read_bstatus)(struct intel_digital_port *intel_dig_port,
351 u8 *bstatus);
352
353 /* Determines whether a repeater is present downstream */
354 int (*repeater_present)(struct intel_digital_port *intel_dig_port,
355 bool *repeater_present);
356
357 /* Reads the receiver's Ri' value */
358 int (*read_ri_prime)(struct intel_digital_port *intel_dig_port, u8 *ri);
359
360 /* Determines if the receiver's KSV FIFO is ready for consumption */
361 int (*read_ksv_ready)(struct intel_digital_port *intel_dig_port,
362 bool *ksv_ready);
363
364 /* Reads the ksv fifo for num_downstream devices */
365 int (*read_ksv_fifo)(struct intel_digital_port *intel_dig_port,
366 int num_downstream, u8 *ksv_fifo);
367
368 /* Reads a 32-bit part of V' from the receiver */
369 int (*read_v_prime_part)(struct intel_digital_port *intel_dig_port,
370 int i, u32 *part);
371
372 /* Enables HDCP signalling on the port */
373 int (*toggle_signalling)(struct intel_digital_port *intel_dig_port,
374 bool enable);
375
376 /* Ensures the link is still protected */
377 bool (*check_link)(struct intel_digital_port *intel_dig_port);
378
379 /* Detects panel's hdcp capability. This is optional for HDMI. */
380 int (*hdcp_capable)(struct intel_digital_port *intel_dig_port,
381 bool *hdcp_capable);
> 382 <<<<<<< HEAD
383 =======
384
385 /* HDCP adaptation(DP/HDMI) required on the port */
386 enum hdcp_wired_protocol protocol;
387
388 /* Detects whether Panel is HDCP2.2 capable */
389 int (*hdcp_2_2_capable)(struct intel_digital_port *intel_dig_port,
390 bool *capable);
391
392 /* Write HDCP2.2 messages.
393 * We are using HDMI msg-id numbers to identify HDCP2 messages, which *
394 * will be remapped to DP AUX registers for DP. */
395 int (*write_2_2_msg)(struct intel_digital_port *intel_dig_port,
396 void *buf, size_t size);
397
398 /* Read HDCP2.2 messages.
399 * We are using HDMI msg-id numbers to identify HDCP2 messages, which *
400 * will be remapped to DP AUX registers for DP. */
401 int (*read_2_2_msg)(struct intel_digital_port *intel_dig_port,
402 u8 msg_id, void *buf, size_t size);
403
404 /*
405 * Implementation of DP HDCP2.2 Errata for the communication of stream
406 * type to Receivers. In DP HDCP2.2 Stream type is one of the input to
407 * the HDCP2.2 Cipher for En/De-Cryption. Not applicable for HDMI.
408 */
409 int (*config_stream_type)(struct intel_digital_port *intel_dig_port,
410 void *buf, size_t size);
411
412 /* HDCP2.2 Link Integrity Check */
413 int (*check_2_2_link)(struct intel_digital_port *intel_dig_port);
> 414 >>>>>>> 4f9e07e71945... drm/doc: Move bridge link target to the right place
415 };
416
---
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