[PATCH RFC v3 5/6] drm: xlnx: zynqmp: Add XV15 and XV20 formats
Hyun Kwon
hyun.kwon at xilinx.com
Sat Feb 10 01:35:55 UTC 2018
Use drm_format_width_bytes() to support non-byte aligned formats.
Signed-off-by: Hyun Kwon <hyun.kwon at xilinx.com>
---
v3
- 2 patches are squashed
---
---
drivers/gpu/drm/xlnx/zynqmp_disp.c | 22 +++++++++++++++++++++-
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/xlnx/zynqmp_disp.c b/drivers/gpu/drm/xlnx/zynqmp_disp.c
index e47d77d..13053fc 100644
--- a/drivers/gpu/drm/xlnx/zynqmp_disp.c
+++ b/drivers/gpu/drm/xlnx/zynqmp_disp.c
@@ -968,6 +968,24 @@ static const struct zynqmp_disp_fmt av_buf_vid_fmts[] = {
.sf[0] = ZYNQMP_DISP_AV_BUF_8BIT_SF,
.sf[1] = ZYNQMP_DISP_AV_BUF_8BIT_SF,
.sf[2] = ZYNQMP_DISP_AV_BUF_8BIT_SF,
+ }, {
+ .drm_fmt = DRM_FORMAT_XV15,
+ .disp_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI_420_10,
+ .rgb = false,
+ .swap = false,
+ .chroma_sub = true,
+ .sf[0] = ZYNQMP_DISP_AV_BUF_10BIT_SF,
+ .sf[1] = ZYNQMP_DISP_AV_BUF_10BIT_SF,
+ .sf[2] = ZYNQMP_DISP_AV_BUF_10BIT_SF,
+ }, {
+ .drm_fmt = DRM_FORMAT_XV20,
+ .disp_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI_10,
+ .rgb = false,
+ .swap = false,
+ .chroma_sub = true,
+ .sf[0] = ZYNQMP_DISP_AV_BUF_10BIT_SF,
+ .sf[1] = ZYNQMP_DISP_AV_BUF_10BIT_SF,
+ .sf[2] = ZYNQMP_DISP_AV_BUF_10BIT_SF,
}
};
@@ -2133,6 +2151,7 @@ static int zynqmp_disp_plane_mode_set(struct drm_plane *plane,
for (i = 0; i < info->num_planes; i++) {
unsigned int width = src_w / (i ? info->hsub : 1);
unsigned int height = src_h / (i ? info->vsub : 1);
+ int width_bytes;
paddr = drm_fb_cma_get_gem_addr(fb, plane->state, i);
if (!paddr) {
@@ -2141,7 +2160,8 @@ static int zynqmp_disp_plane_mode_set(struct drm_plane *plane,
}
layer->dma[i].xt.numf = height;
- layer->dma[i].sgl[0].size = width * info->cpp[i];
+ width_bytes = drm_format_plane_width_bytes(info, i, width);
+ layer->dma[i].sgl[0].size = width_bytes;
layer->dma[i].sgl[0].icg = fb->pitches[i] -
layer->dma[i].sgl[0].size;
layer->dma[i].xt.src_start = paddr;
--
2.7.4
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