[PATCH 2/4] drm/msm: Add new PM4 type7 opcodes

[Sharat Masetty]

This patch adds the following two opcodes:

CP_SET_MARKER opcode is a way to tell CP the current mode of GPU
operation(useful if preemption is in use).

CP_SET_PSEUDO_REG opcode will instruct CP to set a bunch of internal
CP registers, again useful for the preemption save/restore sequence.

Signed-off-by: Sharat Masetty <smasetty at codeaurora.org>
---
 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h b/drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h
index fb605a3..f0fd80e 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h
+++ b/drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h
@@ -202,6 +202,8 @@ enum adreno_pm4_type3_packets {
 	CP_EXEC_CS = 51,
 	CP_PERFCOUNTER_ACTION = 80,
 	CP_SMMU_TABLE_UPDATE = 83,
+	CP_SET_MARKER = 101,
+	CP_SET_PSEUDO_REG = 86,
 	CP_CONTEXT_REG_BUNCH = 92,
 	CP_YIELD_ENABLE = 28,
 	CP_SKIP_IB2_ENABLE_GLOBAL = 29,
-- 
1.9.1