[Intel-gfx] [PATCH v5 02/40] drm: HDMI and DP specific HDCP2.2 defines
C, Ramalingam
ramalingam.c at intel.com
Wed Jul 11 17:59:56 UTC 2018
> -----Original Message-----
> From: Sean Paul [mailto:seanpaul at chromium.org]
> Sent: Tuesday, July 10, 2018 1:53 AM
> To: C, Ramalingam <ramalingam.c at intel.com>
> Cc: intel-gfx at lists.freedesktop.org; dri-devel at lists.freedesktop.org;
> daniel at ffwll.ch; Winkler, Tomas <tomas.winkler at intel.com>; Usyskin,
> Alexander <alexander.usyskin at intel.com>; Shankar, Uma
> <uma.shankar at intel.com>
> Subject: Re: [Intel-gfx] [PATCH v5 02/40] drm: HDMI and DP specific HDCP2.2
> defines
>
> On Wed, Jun 27, 2018 at 02:09:51PM +0530, Ramalingam C wrote:
> > This patch adds HDCP register definitions for HDMI and DP HDCP
> > adaptations.
> >
> > HDMI specific HDCP2.2 register definitions are added into drm_hdcp.h,
> > where as HDCP2.2 register offsets in DPCD offsets are defined at
> > drm_dp_helper.h.
> >
> > v2:
> > bit_field definitions are replaced by macros. [Tomas and Jani]
> > v3:
> > No Changes.
> > v4:
> > Comments style and typos are fixed [Uma]
> > v5:
> > Fix for macros.
> >
> > Signed-off-by: Ramalingam C <ramalingam.c at intel.com>
> > ---
> > include/drm/drm_dp_helper.h | 51
> +++++++++++++++++++++++++++++++++++++++++++++
> > include/drm/drm_hdcp.h | 30 ++++++++++++++++++++++++++
> > 2 files changed, 81 insertions(+)
> >
> > diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> > index c01564991a9f..17e0889d6aaa 100644
> > --- a/include/drm/drm_dp_helper.h
> > +++ b/include/drm/drm_dp_helper.h
> > @@ -904,6 +904,57 @@
> > #define DP_AUX_HDCP_KSV_FIFO 0x6802C
> > #define DP_AUX_HDCP_AINFO 0x6803B
> >
> > +/* DP HDCP2.2 parameter offsets in DPCD address space */
> > +#define DP_HDCP_2_2_REG_RTX_OFFSET 0x69000
> > +#define DP_HDCP_2_2_REG_TXCAPS_OFFSET 0x69008
> > +#define DP_HDCP_2_2_REG_CERT_RX_OFFSET 0x6900B
> > +#define DP_HDCP_2_2_REG_RRX_OFFSET 0x69215
> > +#define DP_HDCP_2_2_REG_RX_CAPS_OFFSET 0x6921D
> > +#define DP_HDCP_2_2_REG_EKPUB_KM_OFFSET 0x69220
> > +#define DP_HDCP_2_2_REG_EKH_KM_OFFSET 0x692A0
> > +#define DP_HDCP_2_2_REG_M_OFFSET 0x692B0
> > +#define DP_HDCP_2_2_REG_HPRIME_OFFSET 0x692C0
> > +#define DP_HDCP_2_2_REG_EKH_KM_RD_OFFSET 0x692E0
> > +#define DP_HDCP_2_2_REG_RN_OFFSET 0x692F0
> > +#define DP_HDCP_2_2_REG_LPRIME_OFFSET 0x692F8
> > +#define DP_HDCP_2_2_REG_EDKEY_KS_OFFSET 0x69318
> > +#define DP_HDCP_2_2_REG_RIV_OFFSET 0x69328
> > +#define DP_HDCP_2_2_REG_RXINFO_OFFSET 0x69330
> > +#define DP_HDCP_2_2_REG_SEQ_NUM_V_OFFSET 0x69332
> > +#define DP_HDCP_2_2_REG_VPRIME_OFFSET 0x69335
> > +#define DP_HDCP_2_2_REG_RECV_ID_LIST_OFFSET 0x69345
> > +#define DP_HDCP_2_2_REG_V_OFFSET 0x693E0
> > +#define DP_HDCP_2_2_REG_SEQ_NUM_M_OFFSET 0x693F0
> > +#define DP_HDCP_2_2_REG_K_OFFSET 0x693F3
> > +#define DP_HDCP_2_2_REG_STREAM_ID_TYPE_OFFSET 0x693F5
> > +#define DP_HDCP_2_2_REG_MPRIME_OFFSET 0x69473
> > +#define DP_HDCP_2_2_REG_RXSTATUS_OFFSET 0x69493
> > +#define DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET 0x69494
> > +#define DP_HDCP_2_2_REG_DBG_OFFSET 0x69518
> > +
> > +/* DP HDCP message start offsets in DPCD address space */
> > +#define DP_HDCP_2_2_AKE_INIT_OFFSET
> DP_HDCP_2_2_REG_RTX_OFFSET
> > +#define DP_HDCP_2_2_AKE_SEND_CERT_OFFSET
> DP_HDCP_2_2_REG_CERT_RX_OFFSET
> > +#define DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET
> DP_HDCP_2_2_REG_EKPUB_KM_OFFSET
> > +#define DP_HDCP_2_2_AKE_STORED_KM_OFFSET
> DP_HDCP_2_2_REG_EKH_KM_OFFSET
> > +#define DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET
> DP_HDCP_2_2_REG_HPRIME_OFFSET
> > +#define DP_HDCP_2_2_AKE_SEND_PAIRING_INFO_OFFSET \
> > +
> DP_HDCP_2_2_REG_EKH_KM_RD_OFFSET
> > +#define DP_HDCP_2_2_LC_INIT_OFFSET
> DP_HDCP_2_2_REG_RN_OFFSET
> > +#define DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET
> DP_HDCP_2_2_REG_LPRIME_OFFSET
> > +#define DP_HDCP_2_2_SKE_SEND_EKS_OFFSET
> DP_HDCP_2_2_REG_EDKEY_KS_OFFSET
> > +#define DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET
> DP_HDCP_2_2_REG_RXINFO_OFFSET
> > +#define DP_HDCP_2_2_REP_SEND_ACK_OFFSET
> DP_HDCP_2_2_REG_V_OFFSET
> > +#define DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET
> DP_HDCP_2_2_REG_SEQ_NUM_M_OFFSET
> > +#define DP_HDCP_2_2_REP_STREAM_READY_OFFSET
> DP_HDCP_2_2_REG_MPRIME_OFFSET
> > +
> > +#define HDCP_2_2_DP_RXSTATUS_LEN 1
> > +#define HDCP_2_2_DP_RXSTATUS_READY(x) ((x) & BIT(0))
> > +#define HDCP_2_2_DP_RXSTATUS_H_PRIME(x) ((x) & BIT(1))
> > +#define HDCP_2_2_DP_RXSTATUS_PAIRING(x) ((x) & BIT(2))
> > +#define HDCP_2_2_DP_RXSTATUS_REAUTH_REQ(x) ((x) & BIT(3))
> > +#define HDCP_2_2_DP_RXSTATUS_LINK_FAILED(x) ((x) & BIT(4))
> > +
> > /* DP 1.2 Sideband message defines */
> > /* peer device type - DP 1.2a Table 2-92 */
> > #define DP_PEER_DEVICE_NONE 0x0
> > diff --git a/include/drm/drm_hdcp.h b/include/drm/drm_hdcp.h index
> > 3e963c5d04b2..2fc6311dc060 100644
> > --- a/include/drm/drm_hdcp.h
> > +++ b/include/drm/drm_hdcp.h
> > @@ -217,4 +217,34 @@ struct hdcp2_dp_errata_stream_type {
> > uint8_t stream_type;
> > } __packed;
> >
> > +/* HDCP2.2 TIMEOUTs in mSec */
>
> Minor nit: it's usually better to add _MS postfix to the var names so it's obvious
> at the point of use what unit the #define is in.
>
> Otherwise,
>
> Reviewed-by: Sean Paul <seanpaul at chromium.org>
Sure I will add _MS. Thanks for the R-b.
Thanks,
Ram.
>
>
> > +#define HDCP_2_2_CERT_TIMEOUT 100
> > +#define HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT 1000
> > +#define HDCP_2_2_HPRIME_PAIRED_TIMEOUT 200
> > +#define HDCP_2_2_PAIRING_TIMEOUT 200
> > +#define HDCP_2_2_HDMI_LPRIME_TIMEOUT 20
> > +#define HDCP_2_2_DP_LPRIME_TIMEOUT 7
> > +#define HDCP_2_2_RECVID_LIST_TIMEOUT 3000
> > +#define HDCP_2_2_STREAM_READY_TIMEOUT 100
> > +
> > +/* HDMI HDCP2.2 Register Offsets */
> > +#define HDCP_2_2_HDMI_REG_VER_OFFSET 0x50
> > +#define HDCP_2_2_HDMI_REG_WR_MSG_OFFSET 0x60
> > +#define HDCP_2_2_HDMI_REG_RXSTATUS_OFFSET 0x70
> > +#define HDCP_2_2_HDMI_REG_RD_MSG_OFFSET 0x80
> > +#define HDCP_2_2_HDMI_REG_DBG_OFFSET 0xC0
> > +
> > +#define HDCP_2_2_HDMI_SUPPORT_MASK BIT(2)
> > +#define HDCP_2_2_RXCAPS_VERSION_VAL 0x2
> > +
> > +#define HDCP_2_2_RX_CAPS_VERSION_VAL 0x02
> > +#define HDCP_2_2_SEQ_NUM_MAX 0xFFFFFF
> > +#define HDCP_2_2_DELAY_BEFORE_ENCRYPTION_EN 200
> > +
> > +/* Below macros take a byte at a time and mask the bit(s) */
> > +#define HDCP_2_2_HDMI_RXSTATUS_LEN 2
> > +#define HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(x) ((x) & 0x3)
> > +#define HDCP_2_2_HDMI_RXSTATUS_READY(x) ((x) & BIT(2))
> > +#define HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(x) ((x) & BIT(3))
> > +
> > #endif
> > --
> > 2.7.4
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx at lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Sean Paul, Software Engineer, Google / Chromium OS
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