[PATCH v2 03/23] drm/dp: DRM DP helper/macros to get DP sink DSC parameters

Tue Jul 31 23:33:15 UTC 2018


>-----Original Message-----
>From: Navare, Manasi D
>Sent: Tuesday, July 31, 2018 2:07 PM
>To: intel-gfx at lists.freedesktop.org
>Cc: Navare, Manasi D <manasi.d.navare at intel.com>; Singh, Gaurav K
><gaurav.k.singh at intel.com>; dri-devel at lists.freedesktop.org; Jani Nikula
><jani.nikula at linux.intel.com>; Ville Syrjala <ville.syrjala at linux.intel.com>;
>Srivatsa, Anusha <anusha.srivatsa at intel.com>
>Subject: [PATCH v2 03/23] drm/dp: DRM DP helper/macros to get DP sink DSC
>parameters
>
>This patch adds inline functions and helpers for obtaining DP sink's supported DSC
>parameters like DSC sink support, eDP compressed BPP supported, maximum slice
>count supported by the sink devices, DSC line buffer bit depth supported on DP
>sink, DSC sink maximum color depth by parsing corresponding DPCD registers.
>
>v4:
>* Add helper to give line buf bit depth (Manasi)
>v3:
>* Use SLICE_CAP_2 for DP (Anusha)
>v2:
>* Add DSC sink support macro (Jani N)
>
>Cc: Gaurav K Singh <gaurav.k.singh at intel.com>
>Cc: dri-devel at lists.freedesktop.org
>Cc: Jani Nikula <jani.nikula at linux.intel.com>
>Cc: Ville Syrjala <ville.syrjala at linux.intel.com>
>Cc: Anusha Srivatsa <anusha.srivatsa at intel.com>
>Signed-off-by: Manasi Navare <manasi.d.navare at intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa at intel.com>

>---
> drivers/gpu/drm/drm_dp_helper.c | 89
>+++++++++++++++++++++++++++++++++++++++++
> include/drm/drm_dp_helper.h     | 30 ++++++++++++++
> 2 files changed, 119 insertions(+)
>
>diff --git a/drivers/gpu/drm/drm_dp_helper.c
>b/drivers/gpu/drm/drm_dp_helper.c index 0cccbcb..7dc61d1 100644
>--- a/drivers/gpu/drm/drm_dp_helper.c
>+++ b/drivers/gpu/drm/drm_dp_helper.c
>@@ -1336,3 +1336,92 @@ int drm_dp_read_desc(struct drm_dp_aux *aux,
>struct drm_dp_desc *desc,
> 	return 0;
> }
> EXPORT_SYMBOL(drm_dp_read_desc);
>+
>+/**
>+ * DRM DP Helpers for DSC
>+ */
>+u8 drm_dp_dsc_sink_max_slice_count(const u8
>dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
>+				   bool is_edp)
>+{
>+	u8 slice_cap1 = dsc_dpcd[DP_DSC_SLICE_CAP_1 - DP_DSC_SUPPORT];
>+
>+	if (is_edp) {
>+		/* For eDP, register DSC_SLICE_CAPABILITIES_1
			NIT : the actual register is DSC_SLICE_CAP_1
 gives slice count
>*/
>+		if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK)
>+			return 4;
>+		if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK)
>+			return 2;
>+		if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK)
>+			return 1;
>+	} else {
>+		/* For DP, use values from DSC_SLICE_CAP_1 and
>DSC_SLICE_CAP2 */
^^^ DSC_SLICE_CAP_2

>+		u8 slice_cap2 = dsc_dpcd[DP_DSC_SLICE_CAP_2 -
>DP_DSC_SUPPORT];
>+
>+		if (slice_cap2 & DP_DSC_24_PER_DP_DSC_SINK)
>+			return 24;
>+		if (slice_cap2 & DP_DSC_20_PER_DP_DSC_SINK)
>+			return 20;
>+		if (slice_cap2 & DP_DSC_16_PER_DP_DSC_SINK)
>+			return 16;
>+		if (slice_cap1 & DP_DSC_12_PER_DP_DSC_SINK)
>+			return 12;
>+		if (slice_cap1 & DP_DSC_10_PER_DP_DSC_SINK)
>+			return 10;
>+		if (slice_cap1 & DP_DSC_8_PER_DP_DSC_SINK)
>+			return 8;
>+		if (slice_cap1 & DP_DSC_6_PER_DP_DSC_SINK)
>+			return 6;
>+		if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK)
>+			return 4;
>+		if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK)
>+			return 2;
>+		if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK)
>+			return 1;
>+	}
>+
>+	return 0;
>+}
>+EXPORT_SYMBOL(drm_dp_dsc_sink_max_slice_count);
>+
>+u8 drm_dp_dsc_sink_line_buf_depth(const u8
>+dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
>+{
>+	u8 line_buf_depth = dsc_dpcd[DP_DSC_LINE_BUF_BIT_DEPTH -
>+DP_DSC_SUPPORT];
>+
>+	switch (line_buf_depth & DP_DSC_LINE_BUF_BIT_DEPTH_MASK) {
>+	case DP_DSC_LINE_BUF_BIT_DEPTH_9:
>+		return 9;
>+	case DP_DSC_LINE_BUF_BIT_DEPTH_10:
>+		return 10;
>+	case DP_DSC_LINE_BUF_BIT_DEPTH_11:
>+		return 11;
>+	case DP_DSC_LINE_BUF_BIT_DEPTH_12:
>+		return 12;
>+	case DP_DSC_LINE_BUF_BIT_DEPTH_13:
>+		return 13;
>+	case DP_DSC_LINE_BUF_BIT_DEPTH_14:
>+		return 14;
>+	case DP_DSC_LINE_BUF_BIT_DEPTH_15:
>+		return 15;
>+	case DP_DSC_LINE_BUF_BIT_DEPTH_16:
>+		return 16;
>+	case DP_DSC_LINE_BUF_BIT_DEPTH_8:
>+		return 8;
>+	}
>+
>+	return 0;
>+}
>+EXPORT_SYMBOL(drm_dp_dsc_sink_line_buf_depth);
>+
>+u8 drm_dp_dsc_sink_max_color_depth(const u8
>+dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
>+{
>+	switch (dsc_dpcd[DP_DSC_DEC_COLOR_DEPTH_CAP -
>DP_DSC_SUPPORT]) {
>+	case DP_DSC_12_BPC:
>+		return 12;
>+	case DP_DSC_10_BPC:
>+		return 10;
>+	case DP_DSC_8_BPC:
>+		return 8;
>+	}
>+	return 0;
>+}
>+EXPORT_SYMBOL(drm_dp_dsc_sink_max_color_depth);
>diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index
>eb0d86c..8c1dbca 100644
>--- a/include/drm/drm_dp_helper.h
>+++ b/include/drm/drm_dp_helper.h
>@@ -1064,6 +1064,36 @@ drm_dp_is_branch(const u8
>dpcd[DP_RECEIVER_CAP_SIZE])
> 	return dpcd[DP_DOWNSTREAMPORT_PRESENT] &
>DP_DWN_STRM_PORT_PRESENT;  }
>
>+/* DP/eDP DSC support */
>+u8 drm_dp_dsc_sink_max_slice_count(const u8
>dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
>+				   bool is_edp);
>+u8 drm_dp_dsc_sink_line_buf_depth(const u8
>+dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]);
>+u8 drm_dp_dsc_sink_max_color_depth(const u8
>+dsc_dpc[DP_DSC_RECEIVER_CAP_SIZE]);
>+
>+static inline bool
>+drm_dp_sink_supports_dsc(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
>+{
>+	return dsc_dpcd[DP_DSC_SUPPORT - DP_DSC_SUPPORT] &
>+		DP_DSC_DECOMPRESSION_IS_SUPPORTED;
>+}
>+
>+static inline u16
>+drm_edp_dsc_sink_output_bpp(const u8
>+dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
>+{
>+	return dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_LOW -
>DP_DSC_SUPPORT] |
>+		(dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_HI -
>DP_DSC_SUPPORT] &
>+		 DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK <<
>+		 DP_DSC_MAX_BITS_PER_PIXEL_HI_SHIFT);
>+}
>+
>+static inline u32
>+drm_dp_dsc_sink_max_slice_width(const u8
>+dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
>+{
>+	/* Max Slicewidth = Number of Pixels * 320 */
>+	return dsc_dpcd[DP_DSC_MAX_SLICE_WIDTH - DP_DSC_SUPPORT] *
>+		DP_DSC_SLICE_WIDTH_MULTIPLIER;
>+}
>+
> /*
>  * DisplayPort AUX channel
>  */
>--
>2.7.4