[DPU PATCH 2/5] drm/msm/dpu: enable cursor plane for primary crtc
Rob Clark
robdclark at gmail.com
Wed Jun 20 17:04:44 UTC 2018
On Wed, Jun 20, 2018 at 12:29 PM, <ryadav at codeaurora.org> wrote:
> On 2018-06-20 19:18, Rob Clark wrote:
>>
>> On Wed, Jun 20, 2018 at 8:50 AM, Sravanthi Kollukuduru
>> <skolluku at codeaurora.org> wrote:
>>>
>>> Reserve one DMA pipe as cursor plane and also, update crtc
>>> support of cursor in crtc_init.
>>
>>
>> hmm, mdp5 in 820 had real cursor planes in hw, did these go away? If
>> so I guess DMA plane is best candidate for cursor..
>
> Hi Rob,
> Yes, the hw cursor support is not present on sdm845.
> The ozone compositor expects cursor planes to be present otherwise cursor is
> not rendered on screen.
> So, we are planning to use one of the DMA pipe for cursor plane.
ok, makes sense
BR,
-R
> Thanks,
> Rajesh
>
>>
>> BR,
>> -R
>>
>>>
>>> Signed-off-by: Sravanthi Kollukuduru <skolluku at codeaurora.org>
>>> ---
>>> drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 7 ++--
>>> drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 3 +-
>>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 53
>>> +++++++++++---------------
>>> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 7 +++-
>>> 4 files changed, 34 insertions(+), 36 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
>>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
>>> index f0aafec..56f6576 100644
>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
>>> @@ -2027,7 +2027,8 @@ static int _dpu_crtc_init_events(struct dpu_crtc
>>> *dpu_crtc)
>>> }
>>>
>>> /* initialize crtc */
>>> -struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane
>>> *plane)
>>> +struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane
>>> *plane,
>>> + struct drm_plane
>>> *cursor_plane)
>>> {
>>> struct drm_crtc *crtc = NULL;
>>> struct dpu_crtc *dpu_crtc = NULL;
>>> @@ -2061,8 +2062,8 @@ struct drm_crtc *dpu_crtc_init(struct drm_device
>>> *dev, struct drm_plane *plane)
>>> dpu_crtc_frame_event_work);
>>> }
>>>
>>> - drm_crtc_init_with_planes(dev, crtc, plane, NULL,
>>> &dpu_crtc_funcs,
>>> - NULL);
>>> + drm_crtc_init_with_planes(dev, crtc, plane,
>>> + cursor_plane, &dpu_crtc_funcs, NULL);
>>>
>>> drm_crtc_helper_add(crtc, &dpu_crtc_helper_funcs);
>>> plane->crtc = crtc;
>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
>>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
>>> index 50c3d4b..b44750d 100644
>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
>>> @@ -366,7 +366,8 @@ void dpu_crtc_complete_commit(struct drm_crtc *crtc,
>>> * @plane: base plane
>>> * @Return: new crtc object or error
>>> */
>>> -struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane
>>> *plane);
>>> +struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane
>>> *plane,
>>> + struct drm_plane *cursor_plane);
>>>
>>> /**
>>> * dpu_crtc_cancel_pending_flip - complete flip for clients on lastclose
>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>>> index f0c2881..c0b8116 100644
>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>>> @@ -29,6 +29,9 @@
>>> BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1) |\
>>> BIT(DPU_SSPP_CDP) | BIT(DPU_SSPP_EXCL_RECT))
>>>
>>> +#define DMA_CURSOR_SDM845_MASK \
>>> + (DMA_SDM845_MASK | BIT(DPU_SSPP_CURSOR))
>>> +
>>> #define MIXER_SDM845_MASK \
>>> (BIT(DPU_MIXER_SOURCESPLIT) | BIT(DPU_DIM_LAYER))
>>>
>>> @@ -169,45 +172,35 @@
>>> static const struct dpu_sspp_sub_blks sdm845_dma_sblk_2 =
>>> _DMA_SBLK("10");
>>> static const struct dpu_sspp_sub_blks sdm845_dma_sblk_3 =
>>> _DMA_SBLK("11");
>>>
>>> -#define SSPP_VIG_BLK(_name, _id, _base, _sblk, _xinid, _clkctrl) \
>>> - { \
>>> - .name = _name, .id = _id, \
>>> - .base = _base, .len = 0x1c8, \
>>> - .features = VIG_SDM845_MASK, \
>>> - .sblk = &_sblk, \
>>> - .xin_id = _xinid, \
>>> - .type = SSPP_TYPE_VIG, \
>>> - .clk_ctrl = _clkctrl \
>>> - }
>>> -
>>> -#define SSPP_DMA_BLK(_name, _id, _base, _sblk, _xinid, _clkctrl) \
>>> +#define SSPP_BLK(_name, _id, _base, _features, \
>>> + _sblk, _xinid, _type, _clkctrl) \
>>> { \
>>> .name = _name, .id = _id, \
>>> .base = _base, .len = 0x1c8, \
>>> - .features = DMA_SDM845_MASK, \
>>> + .features = _features, \
>>> .sblk = &_sblk, \
>>> .xin_id = _xinid, \
>>> - .type = SSPP_TYPE_DMA, \
>>> + .type = _type, \
>>> .clk_ctrl = _clkctrl \
>>> }
>>>
>>> static struct dpu_sspp_cfg sdm845_sspp[] = {
>>> - SSPP_VIG_BLK("sspp_0", SSPP_VIG0, 0x4000,
>>> - sdm845_vig_sblk_0, 0, DPU_CLK_CTRL_VIG0),
>>> - SSPP_VIG_BLK("sspp_1", SSPP_VIG1, 0x6000,
>>> - sdm845_vig_sblk_1, 4, DPU_CLK_CTRL_VIG1),
>>> - SSPP_VIG_BLK("sspp_2", SSPP_VIG2, 0x8000,
>>> - sdm845_vig_sblk_2, 8, DPU_CLK_CTRL_VIG2),
>>> - SSPP_VIG_BLK("sspp_3", SSPP_VIG3, 0xa000,
>>> - sdm845_vig_sblk_3, 12, DPU_CLK_CTRL_VIG3),
>>> - SSPP_DMA_BLK("sspp_8", SSPP_DMA0, 0x24000,
>>> - sdm845_dma_sblk_0, 1, DPU_CLK_CTRL_DMA0),
>>> - SSPP_DMA_BLK("sspp_9", SSPP_DMA1, 0x26000,
>>> - sdm845_dma_sblk_1, 5, DPU_CLK_CTRL_DMA1),
>>> - SSPP_DMA_BLK("sspp_10", SSPP_DMA2, 0x28000,
>>> - sdm845_dma_sblk_2, 9, DPU_CLK_CTRL_CURSOR0),
>>> - SSPP_DMA_BLK("sspp_11", SSPP_DMA3, 0x2a000,
>>> - sdm845_dma_sblk_3, 13, DPU_CLK_CTRL_CURSOR1),
>>> + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SDM845_MASK,
>>> + sdm845_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
>>> + SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, VIG_SDM845_MASK,
>>> + sdm845_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
>>> + SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, VIG_SDM845_MASK,
>>> + sdm845_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
>>> + SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, VIG_SDM845_MASK,
>>> + sdm845_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
>>> + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK,
>>> + sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
>>> + SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_SDM845_MASK,
>>> + sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
>>> + SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_SDM845_MASK,
>>> + sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA,
>>> DPU_CLK_CTRL_CURSOR0),
>>> + SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, DMA_CURSOR_SDM845_MASK,
>>> + sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA,
>>> DPU_CLK_CTRL_CURSOR1),
>>> };
>>>
>>> /*************************************************************
>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
>>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
>>> index 3b17a02..8e2e582 100644
>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
>>> @@ -588,12 +588,13 @@ static int _dpu_kms_drm_obj_init(struct dpu_kms
>>> *dpu_kms)
>>> {
>>> struct drm_device *dev;
>>> struct drm_plane *primary_planes[MAX_PLANES], *plane;
>>> + struct drm_plane *cursor_planes[MAX_PLANES] = { NULL };
>>> struct drm_crtc *crtc;
>>>
>>> struct msm_drm_private *priv;
>>> struct dpu_mdss_cfg *catalog;
>>>
>>> - int primary_planes_idx = 0, i, ret;
>>> + int primary_planes_idx = 0, cursor_planes_idx = 0, i, ret;
>>> int max_crtc_count;
>>>
>>> if (!dpu_kms || !dpu_kms->dev || !dpu_kms->dev->dev) {
>>> @@ -632,6 +633,8 @@ static int _dpu_kms_drm_obj_init(struct dpu_kms
>>> *dpu_kms)
>>>
>>> if (primary)
>>> primary_planes[primary_planes_idx++] = plane;
>>> + if (catalog->sspp[i].features & BIT(DPU_SSPP_CURSOR))
>>> + cursor_planes[cursor_planes_idx++] = plane;
>>>
>>> }
>>>
>>> @@ -639,7 +642,7 @@ static int _dpu_kms_drm_obj_init(struct dpu_kms
>>> *dpu_kms)
>>>
>>> /* Create one CRTC per encoder */
>>> for (i = 0; i < max_crtc_count; i++) {
>>> - crtc = dpu_crtc_init(dev, primary_planes[i]);
>>> + crtc = dpu_crtc_init(dev, primary_planes[i],
>>> cursor_planes[i]);
>>> if (IS_ERR(crtc)) {
>>> ret = PTR_ERR(crtc);
>>> goto fail;
>>> --
>>> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora
>>> Forum,
>>> a Linux Foundation Collaborative Project
>>>
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