[PATCH RFC 01/24] ARM: dts: add gpu node to exynos4

Qiang Yu yuq825 at gmail.com
Fri May 18 09:27:52 UTC 2018


From: Simon Shields <simon at lineageos.org>

v2 (Qiang Yu):
  add vender string to exynos4 mali gpu

Based off a similar commit for the Samsung Mali driver by
Tobias Jakobi <tjakobi at math.uni-bielefeld.de>

Signed-off-by: Simon Shields <simon at lineageos.org>
Signed-off-by: Qiang Yu <yuq825 at gmail.com>
---
 arch/arm/boot/dts/exynos4.dtsi | 33 +++++++++++++++++++++++++++++++++
 1 file changed, 33 insertions(+)

diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index 909a9f2bf5be..7509671c505e 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -731,6 +731,39 @@
 			status = "disabled";
 		};
 
+		gpu: gpu at 13000000 {
+			compatible = "samsung,exynos4-mali", "arm,mali-400";
+			reg = <0x13000000 0x30000>;
+			power-domains = <&pd_g3d>;
+
+			/*
+			 * Propagate VPLL output clock to SCLK_G3D and
+			 * ensure that the DIV_G3D divider is 1.
+			 */
+			assigned-clocks = <&clock CLK_MOUT_G3D1>, <&clock CLK_MOUT_G3D>,
+					  <&clock CLK_FOUT_VPLL>, <&clock CLK_SCLK_G3D>;
+			assigned-clock-parents = <&clock CLK_SCLK_VPLL>,
+						 <&clock CLK_MOUT_G3D1>;
+			assigned-clock-rates = <0>, <0>, <160000000>, <160000000>;
+
+			clocks = <&clock CLK_SCLK_G3D>, <&clock CLK_G3D>;
+			clock-names = "bus", "core";
+
+			interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "ppmmu0", "ppmmu1", "ppmmu2", "ppmmu3",
+					  "gpmmu", "pp0", "pp1", "pp2", "pp3", "gp";
+			status = "disabled";
+		};
+
 		tmu: tmu at 100c0000 {
 			interrupt-parent = <&combiner>;
 			reg = <0x100C0000 0x100>;
-- 
2.17.0



More information about the dri-devel mailing list