[Bug 108591] [CI][DRMTIP] igt at gem_tiled_fence_blits@normal - fail - Failed assertion: linear[i] == start_val

[bugzilla-daemon at freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=108591

Chris Wilson <chris at chris-wilson.co.uk> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|REOPENED                    |RESOLVED
         Resolution|---                         |FIXED

--- Comment #10 from Chris Wilson <chris at chris-wilson.co.uk> ---
commit 7fa28e146994da1e8a4124623d7da97b798ea520 (HEAD -> drm-intel-next-queued,
drm-intel/for-linux-next, drm-intel/drm-intel-next-queued)
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date:   Mon Nov 19 15:41:53 2018 +0000

    drm/i915: Write GPU relocs harder with gen3

    Under moderate amounts of GPU stress, we can observe on Bearlake and
    Pineview (later gen3 models) that we execute the following batch buffer
    before the write into the batch is coherent. Adding extra (tested with
    upto 32x) MI_FLUSH to either the invalidation, flush or both phases does
    not solve the incoherency issue with the relocations, but emitting the
    MI_STORE_DWORD_IMM twice does. So be it.

    Fixes: 7dd4f6729f92 ("drm/i915: Async GPU relocation processing")
    Testcase: igt/gem_tiled_fence_blits # blb/pnv
    Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
    Cc: Joonas Lahtinen <joonas.lahtinen at linux.intel.com>
    Reviewed-by: Joonas Lahtinen <joonas.lahtinen at linux.intel.com>
    Link:
https://patchwork.freedesktop.org/patch/msgid/20181119154153.15327-1-chris@chris-wilson.co.uk

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