[PATCH v2] drm/msm/dsi: fix dsi clock names in DSI 10nm PLL driver

[Sean Paul]

On Thu, Oct 11, 2018, 1:19 PM Abhinav Kumar <abhinavk at codeaurora.org> wrote:

> Fix the dsi clock names in the DSI 10nm PLL driver to
> match the names in the dispcc driver as those are
> according to the clock plan of the chipset.
>
> Changes in v2:
> - Update the clock diagram with the new clock name
>
> Signed-off-by: Abhinav Kumar <abhinavk at codeaurora.org>
>

Reviewed-by: Sean Paul <seanpaul at chromium.org>

(On mobile, apologies for html email)

---
>  drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c
> b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c
> index 41bec57..3120562 100644
> --- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c
> +++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c
> @@ -17,7 +17,7 @@
>   *                              |                |
>   *                              |                |
>   *                 +---------+  |  +----------+  |  +----+
> - *  dsi0vco_clk ---| out_div |--o--| divl_3_0 |--o--| /8 |-- dsi0pllbyte
> + *  dsi0vco_clk ---| out_div |--o--| divl_3_0 |--o--| /8 |--
> dsi0_phy_pll_out_byteclk
>   *                 +---------+  |  +----------+  |  +----+
>   *                              |                |
>   *                              |                |
>  dsi0_pll_by_2_bit_clk
> @@ -25,7 +25,7 @@
>   *                              |                |  +----+  |  |\
> dsi0_pclk_mux
>   *                              |                |--| /2 |--o--| \   |
>   *                              |                |  +----+     |  \  |
> +---------+
> - *                              |                --------------|  |--o--|
> div_7_4 |-- dsi0pll
> + *                              |                --------------|  |--o--|
> div_7_4 |-- dsi0_phy_pll_out_dsiclk
>   *                              |------------------------------|  /
>  +---------+
>   *                              |          +-----+             | /
>   *                              -----------| /4? |--o----------|/
> @@ -690,7 +690,7 @@ static int pll_10nm_register(struct dsi_pll_10nm
> *pll_10nm)
>
>         hws[num++] = hw;
>
> -       snprintf(clk_name, 32, "dsi%dpllbyte", pll_10nm->id);
> +       snprintf(clk_name, 32, "dsi%d_phy_pll_out_byteclk", pll_10nm->id);
>         snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_10nm->id);
>
>         /* DSI Byte clock = VCO_CLK / OUT_DIV / BIT_DIV / 8 */
> @@ -739,7 +739,7 @@ static int pll_10nm_register(struct dsi_pll_10nm
> *pll_10nm)
>
>         hws[num++] = hw;
>
> -       snprintf(clk_name, 32, "dsi%dpll", pll_10nm->id);
> +       snprintf(clk_name, 32, "dsi%d_phy_pll_out_dsiclk", pll_10nm->id);
>         snprintf(parent, 32, "dsi%d_pclk_mux", pll_10nm->id);
>
>         /* PIX CLK DIV : DIV_CTRL_7_4*/
> --
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
>
>
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