[PATCH v5 13/19] drm/msm/dpu: clean up destination scaler residue
Jeykumar Sankaran
jsanka at codeaurora.org
Thu Sep 6 02:08:22 UTC 2018
Destination scaling(DS) is a Snapdragon hardware feature to
scale up the display ROI after layer blending. DPU driver doesn't
support programming of DS blocks yet. This change cleans up the
residual code present in catalog and RM for DS block handling.
Support for the same can be added back when the feature is
formally implemented.
changes in v5:
- introduced in the series
Signed-off-by: Jeykumar Sankaran <jsanka at codeaurora.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 42 +++++---------------------
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 40 ------------------------
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 7 -----
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 10 ------
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 2 --
5 files changed, 7 insertions(+), 94 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index c04f3f3..9f71861 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -74,7 +74,6 @@
.base = 0x0, .len = 0x45C,
.features = 0,
.highest_bank_bit = 0x2,
- .has_dest_scaler = true,
.clk_ctrls[DPU_CLK_CTRL_VIG0] = {
.reg_off = 0x2AC, .bit_off = 0},
.clk_ctrls[DPU_CLK_CTRL_VIG1] = {
@@ -220,48 +219,23 @@
},
};
-#define LM_BLK(_name, _id, _base, _ds, _pp, _lmpair) \
+#define LM_BLK(_name, _id, _base, _pp, _lmpair) \
{ \
.name = _name, .id = _id, \
.base = _base, .len = 0x320, \
.features = MIXER_SDM845_MASK, \
.sblk = &sdm845_lm_sblk, \
- .ds = _ds, \
.pingpong = _pp, \
.lm_pair_mask = (1 << _lmpair) \
}
static struct dpu_lm_cfg sdm845_lm[] = {
- LM_BLK("lm_0", LM_0, 0x44000, DS_0, PINGPONG_0, LM_1),
- LM_BLK("lm_1", LM_1, 0x45000, DS_1, PINGPONG_1, LM_0),
- LM_BLK("lm_2", LM_2, 0x46000, DS_MAX, PINGPONG_2, LM_5),
- LM_BLK("lm_3", LM_3, 0x0, DS_MAX, PINGPONG_MAX, 0),
- LM_BLK("lm_4", LM_4, 0x0, DS_MAX, PINGPONG_MAX, 0),
- LM_BLK("lm_5", LM_5, 0x49000, DS_MAX, PINGPONG_3, LM_2),
-};
-
-/*************************************************************
- * DS sub blocks config
- *************************************************************/
-static const struct dpu_ds_top_cfg sdm845_ds_top = {
- .name = "ds_top_0", .id = DS_TOP,
- .base = 0x60000, .len = 0xc,
- .maxinputwidth = DEFAULT_DPU_LINE_WIDTH,
- .maxoutputwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
- .maxupscale = MAX_UPSCALE_RATIO,
-};
-
-#define DS_BLK(_name, _id, _base) \
- {\
- .name = _name, .id = _id, \
- .base = _base, .len = 0x800, \
- .features = DPU_SSPP_SCALER_QSEED3, \
- .top = &sdm845_ds_top \
- }
-
-static struct dpu_ds_cfg sdm845_ds[] = {
- DS_BLK("ds_0", DS_0, 0x800),
- DS_BLK("ds_1", DS_1, 0x1000),
+ LM_BLK("lm_0", LM_0, 0x44000, PINGPONG_0, LM_1),
+ LM_BLK("lm_1", LM_1, 0x45000, PINGPONG_1, LM_0),
+ LM_BLK("lm_2", LM_2, 0x46000, PINGPONG_2, LM_5),
+ LM_BLK("lm_3", LM_3, 0x0, PINGPONG_MAX, 0),
+ LM_BLK("lm_4", LM_4, 0x0, PINGPONG_MAX, 0),
+ LM_BLK("lm_5", LM_5, 0x49000, PINGPONG_3, LM_2),
};
/*************************************************************
@@ -454,8 +428,6 @@ static void sdm845_cfg_init(struct dpu_mdss_cfg *dpu_cfg)
.sspp = sdm845_sspp,
.mixer_count = ARRAY_SIZE(sdm845_lm),
.mixer = sdm845_lm,
- .ds_count = ARRAY_SIZE(sdm845_ds),
- .ds = sdm845_ds,
.pingpong_count = ARRAY_SIZE(sdm845_pp),
.pingpong = sdm845_pp,
.cdm_count = ARRAY_SIZE(sdm845_cdm),
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index f0cb0d4..2da803c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -428,7 +428,6 @@ struct dpu_clk_ctrl_reg {
* @highest_bank_bit: UBWC parameter
* @ubwc_static: ubwc static configuration
* @ubwc_swizzle: ubwc default swizzle setting
- * @has_dest_scaler: indicates support of destination scaler
* @clk_ctrls clock control register definition
*/
struct dpu_mdp_cfg {
@@ -436,7 +435,6 @@ struct dpu_mdp_cfg {
u32 highest_bank_bit;
u32 ubwc_static;
u32 ubwc_swizzle;
- bool has_dest_scaler;
struct dpu_clk_ctrl_reg clk_ctrls[DPU_CLK_CTRL_MAX];
};
@@ -474,50 +472,16 @@ struct dpu_sspp_cfg {
* @features bit mask identifying sub-blocks/features
* @sblk: LM Sub-blocks information
* @pingpong: ID of connected PingPong, PINGPONG_MAX if unsupported
- * @ds: ID of connected DS, DS_MAX if unsupported
* @lm_pair_mask: Bitmask of LMs that can be controlled by same CTL
*/
struct dpu_lm_cfg {
DPU_HW_BLK_INFO;
const struct dpu_lm_sub_blks *sblk;
u32 pingpong;
- u32 ds;
unsigned long lm_pair_mask;
};
/**
- * struct dpu_ds_top_cfg - information of dest scaler top
- * @id enum identifying this block
- * @base register offset of this block
- * @features bit mask identifying features
- * @version hw version of dest scaler
- * @maxinputwidth maximum input line width
- * @maxoutputwidth maximum output line width
- * @maxupscale maximum upscale ratio
- */
-struct dpu_ds_top_cfg {
- DPU_HW_BLK_INFO;
- u32 version;
- u32 maxinputwidth;
- u32 maxoutputwidth;
- u32 maxupscale;
-};
-
-/**
- * struct dpu_ds_cfg - information of dest scaler blocks
- * @id enum identifying this block
- * @base register offset wrt DS top offset
- * @features bit mask identifying features
- * @version hw version of the qseed block
- * @top DS top information
- */
-struct dpu_ds_cfg {
- DPU_HW_BLK_INFO;
- u32 version;
- const struct dpu_ds_top_cfg *top;
-};
-
-/**
* struct dpu_pingpong_cfg - information of PING-PONG blocks
* @id enum identifying this block
* @base register offset of this block
@@ -728,9 +692,6 @@ struct dpu_mdss_cfg {
u32 mixer_count;
struct dpu_lm_cfg *mixer;
- u32 ds_count;
- struct dpu_ds_cfg *ds;
-
u32 pingpong_count;
struct dpu_pingpong_cfg *pingpong;
@@ -771,7 +732,6 @@ struct dpu_mdss_hw_cfg_handler {
#define BLK_DMA(s) ((s)->dma)
#define BLK_CURSOR(s) ((s)->cursor)
#define BLK_MIXER(s) ((s)->mixer)
-#define BLK_DS(s) ((s)->ds)
#define BLK_PINGPONG(s) ((s)->pingpong)
#define BLK_CDM(s) ((s)->cdm)
#define BLK_INTF(s) ((s)->intf)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
index 35e6bf9..1646812 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
@@ -173,13 +173,6 @@ enum dpu_dspp {
DSPP_MAX
};
-enum dpu_ds {
- DS_TOP,
- DS_0,
- DS_1,
- DS_MAX
-};
-
enum dpu_ctl {
CTL_0 = 1,
CTL_1,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index 13c0a36..0b43193 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
@@ -27,7 +27,6 @@
#define RM_RQ_LOCK(r) ((r)->top_ctrl & BIT(DPU_RM_TOPCTL_RESERVE_LOCK))
#define RM_RQ_CLEAR(r) ((r)->top_ctrl & BIT(DPU_RM_TOPCTL_RESERVE_CLEAR))
-#define RM_RQ_DS(r) ((r)->top_ctrl & BIT(DPU_RM_TOPCTL_DS))
#define RM_IS_TOPOLOGY_MATCH(t, r) ((t).num_lm == (r).num_lm && \
(t).num_comp_enc == (r).num_enc && \
(t).num_intf == (r).num_intf)
@@ -820,15 +819,6 @@ static int _dpu_rm_populate_requirements(
return -EINVAL;
}
- /**
- * Set the requirement based on caps if not set from user space
- * This will ensure to select LM tied with DS blocks
- * Currently, DS blocks are tied with LM 0 and LM 1 (primary display)
- */
- if (!RM_RQ_DS(reqs) && rm->hw_mdp->caps->has_dest_scaler &&
- conn_state->connector->connector_type == DRM_MODE_CONNECTOR_DSI)
- reqs->top_ctrl |= BIT(DPU_RM_TOPCTL_DS);
-
DRM_DEBUG_KMS("top_ctrl: 0x%llX num_h_tiles: %d\n", reqs->top_ctrl,
reqs->hw_res.display_num_of_h_tiles);
DRM_DEBUG_KMS("num_lm: %d num_ctl: %d topology: %d split_display: %d\n",
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
index ffd1841..89355d0 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
@@ -45,12 +45,10 @@ enum dpu_rm_topology_name {
* release any reservation held by this display.
* Normal behavior would not impact the
* reservation list during the AtomicTest phase.
- * @DPU_RM_TOPCTL_DS : Require layer mixers with DS capabilities
*/
enum dpu_rm_topology_control {
DPU_RM_TOPCTL_RESERVE_LOCK,
DPU_RM_TOPCTL_RESERVE_CLEAR,
- DPU_RM_TOPCTL_DS,
};
/**
--
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