[PATCH v2 13/16] arm64: dts: renesas: r8a77990: Add display output support
Laurent Pinchart
laurent.pinchart at ideasonboard.com
Mon Sep 17 08:47:15 UTC 2018
Hi Simon,
On Monday, 17 September 2018 11:14:20 EEST Simon Horman wrote:
> On Mon, Sep 17, 2018 at 09:50:55AM +0200, Simon Horman wrote:
> > On Fri, Sep 14, 2018 at 12:10:43PM +0300, Laurent Pinchart wrote:
> > > The R8A77990 (E3) platform has one RGB output and two LVDS outputs
> > > connected to the DU. Add the DT nodes for the DU, LVDS encoders and
> > > supporting VSP and FCP.
> > >
> > > Signed-off-by: Laurent Pinchart
> > > <laurent.pinchart+renesas at ideasonboard.com>
> > > Tested-by: Jacopo Mondi <jacopo+renesas at jmondi.org>
> > > ---
> > >
> > > arch/arm64/boot/dts/renesas/r8a77990.dtsi | 167 +++++++++++++++++++++++
> > > 1 file changed, 167 insertions(+)
> > >
> > > diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi
> > > b/arch/arm64/boot/dts/renesas/r8a77990.dtsi index
> > > abb14af76c0e..600074ca3ee5 100644
> > > --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi
> > > +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
> > > @@ -537,6 +537,173 @@
> > >
> > > resets = <&cpg 408>;
> > >
> > > };
> >
> > These nodes should be placed after the gic to preserve the sorting
> > of nodes by bus address and then IP block.
> >
> > > + vspb0: vsp at fe960000 {
> > > + compatible = "renesas,vsp2";
> > > + reg = <0 0xfe960000 0 0x8000>;
> > > + interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
> > > + clocks = <&cpg CPG_MOD 626>;
> > > + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
> > > + resets = <&cpg 626>;
> > > + renesas,fcp = <&fcpvb0>;
> > > + };
> > > +
> > > + fcpvb0: fcp at fe96f000 {
> > > + compatible = "renesas,fcpv";
> > > + reg = <0 0xfe96f000 0 0x200>;
> > > + clocks = <&cpg CPG_MOD 607>;
> > > + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
> > > + resets = <&cpg 607>;
> > > + iommus = <&ipmmu_vp0 5>;
> > > + };
> > > +
> > > + vspi0: vsp at fe9a0000 {
> > > + compatible = "renesas,vsp2";
> > > + reg = <0 0xfe9a0000 0 0x8000>;
> > > + interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
> > > + clocks = <&cpg CPG_MOD 622>;
> >
> > R-Car Series, 3rd Generation, v1.00, Table Table 8A.21 indicates
> > that this clock should be <&cpg CPG_MOD 631>. The clock above is
> > (according to my reading of the documentation) correctly
> > used for vspd1 below.
> >
> > > + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
> > > + resets = <&cpg 631>;
> > > + renesas,fcp = <&fcpvi0>;
> > > + };
> > > +
> > > + fcpvi0: fcp at fe9af000 {
> > > + compatible = "renesas,fcpv";
> > > + reg = <0 0xfe9af000 0 0x200>;
> > > + clocks = <&cpg CPG_MOD 611>;
> > > + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
> > > + resets = <&cpg 611>;
> > > + iommus = <&ipmmu_vp0 8>;
> > > + };
> > > +
> > > + vspd0: vsp at fea20000 {
> > > + compatible = "renesas,vsp2";
> > > + reg = <0 0xfea20000 0 0x7000>;
> > > + interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
> > > + clocks = <&cpg CPG_MOD 623>;
> > > + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
> > > + resets = <&cpg 623>;
> > > + renesas,fcp = <&fcpvd0>;
> > > + };
> > > +
> > > + fcpvd0: fcp at fea27000 {
> > > + compatible = "renesas,fcpv";
> > > + reg = <0 0xfea27000 0 0x200>;
> > > + clocks = <&cpg CPG_MOD 603>;
> > > + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
> > > + resets = <&cpg 603>;
> > > + iommus = <&ipmmu_vi0 8>;
> > > + };
> > > +
> > > + vspd1: vsp at fea28000 {
> > > + compatible = "renesas,vsp2";
> > > + reg = <0 0xfea28000 0 0x7000>;
> > > + interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
> > > + clocks = <&cpg CPG_MOD 622>;
> > > + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
> > > + resets = <&cpg 622>;
> > > + renesas,fcp = <&fcpvd1>;
> > > + };
> > > +
> > > + fcpvd1: fcp at fea2f000 {
> > > + compatible = "renesas,fcpv";
> > > + reg = <0 0xfea2f000 0 0x200>;
> > > + clocks = <&cpg CPG_MOD 602>;
> > > + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
> > > + resets = <&cpg 602>;
> > > + iommus = <&ipmmu_vi0 9>;
> > > + };
> > > +
> > > + du: display at feb00000 {
> > > + compatible = "renesas,du-r8a77990";
> > > + reg = <0 0xfeb00000 0 0x80000>;
> > > + interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
> > > + clocks = <&cpg CPG_MOD 724>,
> > > + <&cpg CPG_MOD 723>;
> > > + clock-names = "du.0", "du.1";
> > > + vsps = <&vspd0 0 &vspd1 0>;
> > > + status = "disabled";
> > > +
> > > + ports {
> > > + #address-cells = <1>;
> > > + #size-cells = <0>;
> > > +
> > > + port at 0 {
> > > + reg = <0>;
> > > + du_out_rgb: endpoint {
> > > + };
> > > + };
> > > +
> > > + port at 1 {
> > > + reg = <1>;
> > > + du_out_lvds0: endpoint {
> > > + remote-endpoint = <&lvds0_in>;
> > > + };
> > > + };
> > > +
> > > + port at 2 {
> > > + reg = <2>;
> > > + du_out_lvds1: endpoint {
> > > + remote-endpoint = <&lvds1_in>;
> > > + };
> > > + };
> > > + };
> > > + };
> > > +
> > > + lvds0: lvds-encoder at feb90000 {
> > > + compatible = "renesas,r8a77990-lvds";
> > > + reg = <0 0xfeb90000 0 0x20>;
> > > + clocks = <&cpg CPG_MOD 727>;
> > > + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
> > > + resets = <&cpg 727>;
> > > + status = "disabled";
> > > +
> > > + ports {
> > > + #address-cells = <1>;
> > > + #size-cells = <0>;
> > > +
> > > + port at 0 {
> > > + reg = <0>;
> > > + lvds0_in: endpoint {
> > > + remote-endpoint = <&du_out_lvds0>;
> > > + };
> > > + };
> > > +
> > > + port at 1 {
> > > + reg = <1>;
> > > + lvds0_out: endpoint {
> > > + };
> > > + };
> > > + };
> > > + };
> > > +
> > > + lvds1: lvds-encoder at feb90100 {
> > > + compatible = "renesas,r8a77990-lvds";
> > > + reg = <0 0xfeb90100 0 0x20>;
> > > + clocks = <&cpg CPG_MOD 727>;
> > > + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
> > > + resets = <&cpg 726>;
>
> Also, is the missmatch between the index for the clock and reset
> intentional?
It is. According to the datasheet, the two LVDS encoders have different module
stop bits, but share the same reset (lovely hardware design, it will be fun to
support that in the driver :-S).
> > > + status = "disabled";
> > > +
> > > + ports {
> > > + #address-cells = <1>;
> > > + #size-cells = <0>;
> > > +
> > > + port at 0 {
> > > + reg = <0>;
> > > + lvds1_in: endpoint {
> > > + remote-endpoint = <&du_out_lvds1>;
> > > + };
> > > + };
> > > +
> > > + port at 1 {
> > > + reg = <1>;
> > > + lvds1_out: endpoint {
> > > + };
> > > + };
> > > + };
> > > + };
> > > +
> > > prr: chipid at fff00044 {
> > > compatible = "renesas,prr";
> > > reg = <0 0xfff00044 0 4>;
--
Regards,
Laurent Pinchart
More information about the dri-devel
mailing list