[PATCH] drm/msm/A6xx: Send the right perf index value to GMU

[Sharat Masetty]

The index of the perf table was being set in the wrong bit position
in the register. With this fix, the GPU clock can be seen running at
desired frequency.

Signed-off-by: Sharat Masetty <smasetty at codeaurora.org>
---
 drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
index 3762c8d..421456e1 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
@@ -78,7 +78,7 @@ static void __a6xx_gmu_set_freq(struct a6xx_gmu *gmu, int index)
 	gmu_write(gmu, REG_A6XX_GMU_DCVS_ACK_OPTION, 0);
 
 	gmu_write(gmu, REG_A6XX_GMU_DCVS_PERF_SETTING,
-		((index << 24) & 0xff) | (3 & 0xf));
+		((3 & 0xf) << 28) | (index & 0xff));
 
 	/*
 	 * Send an invalid index as a vote for the bus bandwidth and let the
-- 
1.9.1