[radeon-alex:drm-next-5.2-wip 477/477] drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:156:13: sparse: incorrect type in assignment (different address spaces)
kbuild test robot
lkp at intel.com
Wed Apr 3 11:35:52 UTC 2019
tree: git://people.freedesktop.org/~agd5f/linux.git drm-next-5.2-wip
head: 02b76b4ae25fd4c0ac0bf07155cc642f9eeccbbd
commit: 02b76b4ae25fd4c0ac0bf07155cc642f9eeccbbd [477/477] drm/amdgpu: fix old fence check in amdgpu_fence_emit
reproduce:
# apt-get install sparse
git checkout 02b76b4ae25fd4c0ac0bf07155cc642f9eeccbbd
make ARCH=x86_64 allmodconfig
make C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__'
sparse warnings: (new ones prefixed by >>)
drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:101:32: sparse: incorrect type in assignment (different base types) @@ expected unsigned int volatile [unsigned] [usertype] <noident> @@ got latile [unsigned] [usertype] <noident> @@
drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:101:32: expected unsigned int volatile [unsigned] [usertype] <noident>
drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:101:32: got restricted __le32 [usertype] <noident>
drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:118:23: sparse: cast to restricted __le32
>> drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:156:13: sparse: incorrect type in assignment (different address spaces) @@ expected struct dma_fence [noderef] <asn:4>**ptr @@ got [noderef] <asn:4>**ptr @@
drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:156:13: expected struct dma_fence [noderef] <asn:4>**ptr
drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:156:13: got struct dma_fence **
drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:262:25: sparse: incompatible types in comparison expression (different address spaces)
drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:263:17: sparse: incompatible types in comparison expression (different address spaces)
drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:316:17: sparse: incompatible types in comparison expression (different address spaces)
include/linux/slab.h:664:13: sparse: undefined identifier '__builtin_mul_overflow'
drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:697:28: sparse: cast to restricted __le32
drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:700:28: sparse: cast to restricted __le32
drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:703:28: sparse: cast to restricted __le32
include/linux/slab.h:664:13: sparse: call with no type!
vim +156 drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
22e5a2f4 Christian König 2016-03-11 87
d38ceaf9 Alex Deucher 2015-04-20 88 /**
d38ceaf9 Alex Deucher 2015-04-20 89 * amdgpu_fence_write - write a fence value
d38ceaf9 Alex Deucher 2015-04-20 90 *
d38ceaf9 Alex Deucher 2015-04-20 91 * @ring: ring the fence is associated with
d38ceaf9 Alex Deucher 2015-04-20 92 * @seq: sequence number to write
d38ceaf9 Alex Deucher 2015-04-20 93 *
d38ceaf9 Alex Deucher 2015-04-20 94 * Writes a fence value to memory (all asics).
d38ceaf9 Alex Deucher 2015-04-20 95 */
d38ceaf9 Alex Deucher 2015-04-20 96 static void amdgpu_fence_write(struct amdgpu_ring *ring, u32 seq)
d38ceaf9 Alex Deucher 2015-04-20 97 {
d38ceaf9 Alex Deucher 2015-04-20 98 struct amdgpu_fence_driver *drv = &ring->fence_drv;
d38ceaf9 Alex Deucher 2015-04-20 99
d38ceaf9 Alex Deucher 2015-04-20 100 if (drv->cpu_addr)
d38ceaf9 Alex Deucher 2015-04-20 @101 *drv->cpu_addr = cpu_to_le32(seq);
d38ceaf9 Alex Deucher 2015-04-20 102 }
d38ceaf9 Alex Deucher 2015-04-20 103
d38ceaf9 Alex Deucher 2015-04-20 104 /**
d38ceaf9 Alex Deucher 2015-04-20 105 * amdgpu_fence_read - read a fence value
d38ceaf9 Alex Deucher 2015-04-20 106 *
d38ceaf9 Alex Deucher 2015-04-20 107 * @ring: ring the fence is associated with
d38ceaf9 Alex Deucher 2015-04-20 108 *
d38ceaf9 Alex Deucher 2015-04-20 109 * Reads a fence value from memory (all asics).
d38ceaf9 Alex Deucher 2015-04-20 110 * Returns the value of the fence read from memory.
d38ceaf9 Alex Deucher 2015-04-20 111 */
d38ceaf9 Alex Deucher 2015-04-20 112 static u32 amdgpu_fence_read(struct amdgpu_ring *ring)
d38ceaf9 Alex Deucher 2015-04-20 113 {
d38ceaf9 Alex Deucher 2015-04-20 114 struct amdgpu_fence_driver *drv = &ring->fence_drv;
d38ceaf9 Alex Deucher 2015-04-20 115 u32 seq = 0;
d38ceaf9 Alex Deucher 2015-04-20 116
d38ceaf9 Alex Deucher 2015-04-20 117 if (drv->cpu_addr)
d38ceaf9 Alex Deucher 2015-04-20 118 seq = le32_to_cpu(*drv->cpu_addr);
d38ceaf9 Alex Deucher 2015-04-20 119 else
742c085f Christian König 2016-03-14 120 seq = atomic_read(&drv->last_seq);
d38ceaf9 Alex Deucher 2015-04-20 121
d38ceaf9 Alex Deucher 2015-04-20 122 return seq;
d38ceaf9 Alex Deucher 2015-04-20 123 }
d38ceaf9 Alex Deucher 2015-04-20 124
d38ceaf9 Alex Deucher 2015-04-20 125 /**
d38ceaf9 Alex Deucher 2015-04-20 126 * amdgpu_fence_emit - emit a fence on the requested ring
d38ceaf9 Alex Deucher 2015-04-20 127 *
d38ceaf9 Alex Deucher 2015-04-20 128 * @ring: ring the fence is associated with
364beb2c Christian König 2016-02-16 129 * @f: resulting fence object
d38ceaf9 Alex Deucher 2015-04-20 130 *
d38ceaf9 Alex Deucher 2015-04-20 131 * Emits a fence command on the requested ring (all asics).
d38ceaf9 Alex Deucher 2015-04-20 132 * Returns 0 on success, -ENOMEM on failure.
d38ceaf9 Alex Deucher 2015-04-20 133 */
d240cd9e Marek Olšák 2018-04-03 134 int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **f,
d240cd9e Marek Olšák 2018-04-03 135 unsigned flags)
d38ceaf9 Alex Deucher 2015-04-20 136 {
d38ceaf9 Alex Deucher 2015-04-20 137 struct amdgpu_device *adev = ring->adev;
364beb2c Christian König 2016-02-16 138 struct amdgpu_fence *fence;
02b76b4a Christian König 2019-03-29 139 struct dma_fence __rcu **ptr;
742c085f Christian König 2016-03-14 140 uint32_t seq;
02b76b4a Christian König 2019-03-29 141 int r;
d38ceaf9 Alex Deucher 2015-04-20 142
364beb2c Christian König 2016-02-16 143 fence = kmem_cache_alloc(amdgpu_fence_slab, GFP_KERNEL);
364beb2c Christian König 2016-02-16 144 if (fence == NULL)
d38ceaf9 Alex Deucher 2015-04-20 145 return -ENOMEM;
364beb2c Christian König 2016-02-16 146
742c085f Christian König 2016-03-14 147 seq = ++ring->fence_drv.sync_seq;
364beb2c Christian König 2016-02-16 148 fence->ring = ring;
f54d1867 Chris Wilson 2016-10-25 149 dma_fence_init(&fence->base, &amdgpu_fence_ops,
4a7d74f1 Christian König 2016-03-14 150 &ring->fence_drv.lock,
7f06c236 monk.liu 2015-07-30 151 adev->fence_context + ring->idx,
742c085f Christian König 2016-03-14 152 seq);
890ee23f Chunming Zhou 2015-06-01 153 amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr,
d240cd9e Marek Olšák 2018-04-03 154 seq, flags | AMDGPU_FENCE_FLAG_INT);
c89377d1 Christian König 2016-03-13 155
742c085f Christian König 2016-03-14 @156 ptr = &ring->fence_drv.fences[seq & ring->fence_drv.num_fences_mask];
02b76b4a Christian König 2019-03-29 157 if (unlikely(rcu_dereference_protected(*ptr, 1))) {
02b76b4a Christian König 2019-03-29 158 struct dma_fence *old;
02b76b4a Christian König 2019-03-29 159
02b76b4a Christian König 2019-03-29 160 rcu_read_lock();
02b76b4a Christian König 2019-03-29 161 old = dma_fence_get_rcu_safe(ptr);
02b76b4a Christian König 2019-03-29 162 rcu_read_unlock();
02b76b4a Christian König 2019-03-29 163
02b76b4a Christian König 2019-03-29 164 if (old) {
02b76b4a Christian König 2019-03-29 165 r = dma_fence_wait(old, false);
02b76b4a Christian König 2019-03-29 166 dma_fence_put(old);
02b76b4a Christian König 2019-03-29 167 if (r)
02b76b4a Christian König 2019-03-29 168 return r;
02b76b4a Christian König 2019-03-29 169 }
02b76b4a Christian König 2019-03-29 170 }
02b76b4a Christian König 2019-03-29 171
c89377d1 Christian König 2016-03-13 172 /* This function can't be called concurrently anyway, otherwise
c89377d1 Christian König 2016-03-13 173 * emitting the fence would mess up the hardware ring buffer.
c89377d1 Christian König 2016-03-13 174 */
f54d1867 Chris Wilson 2016-10-25 175 rcu_assign_pointer(*ptr, dma_fence_get(&fence->base));
c89377d1 Christian König 2016-03-13 176
364beb2c Christian König 2016-02-16 177 *f = &fence->base;
c89377d1 Christian König 2016-03-13 178
d38ceaf9 Alex Deucher 2015-04-20 179 return 0;
d38ceaf9 Alex Deucher 2015-04-20 180 }
d38ceaf9 Alex Deucher 2015-04-20 181
:::::: The code at line 156 was first introduced by commit
:::::: 742c085fa86345ae9de259c7f15c652322da4e83 drm/amdgpu: switch back to 32bit hw fences v2
:::::: TO: Christian König <christian.koenig at amd.com>
:::::: CC: Alex Deucher <alexander.deucher at amd.com>
---
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