[PATCH v5 0/7] sunxi: Add DT representation for the MBUS controller

[Chen-Yu Tsai]

On Mon, Apr 8, 2019 at 4:21 PM Maxime Ripard <maxime.ripard at bootlin.com> wrote:
>
> On Mon, Apr 08, 2019 at 04:14:53PM +0800, Chen-Yu Tsai wrote:
> > On Mon, Apr 8, 2019 at 4:11 PM Maxime Ripard <maxime.ripard at bootlin.com> wrote:
> > >
> > > On Sat, Apr 06, 2019 at 01:06:07AM -0500, Rob Herring wrote:
> > > > On Mon, Apr 01, 2019 at 10:56:40AM +0200, Maxime Ripard wrote:
> > > > > Hi,
> > > > >
> > > > > We've had for quite some time to hack around in our drivers to take into
> > > > > account the fact that our DMA accesses are not done through the parent
> > > > > node, but through another bus with a different mapping than the CPU for the
> > > > > RAM (0 instead of 0x40000000 for most SoCs).
> > > > >
> > > > > After some discussion after the submission of a camera device suffering of
> > > > > the same hacks, I've decided to put together a serie that introduce a
> > > > > special interconnect name called "dma" that that allows to express the DMA
> > > > > relationship between a master and its bus, even if they are not direct
> > > > > parents in the DT.
> > > > >
> > > > > Let me know what you think,
> > > > > Maxime
> > > >
> > > > LGTM.
> > > >
> > > > How do you propose merging this? I can take 1-5, and 6 and 7 thru
> > > > arm-soc?
> > >
> > > You can merge 1-4, and I'll merge 5 through drm-misc and 6-7 through
> > > arm-soc
> >
> > Wouldn't there be some runtime dependency between 3, 4, and 5?
>
> What issue did you have in mind?
>
> I guess the only issue would be if we have the new DT properties, but
> not the new core code. But that seems pretty unlikely, since each of
> the trees will work independently, and next should have all of them.

I got it wrong. Even in your case since the interconnect property is
ignored, and the driver would just fall back to using the fixed offset.

Sorry for the noise.

ChenYu