[Bug 110347] pp_od_clk_voltage mV cap ignored

[bugzilla-daemon at freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=110347

--- Comment #4 from bednarczyk.pawel at outlook.com ---
For whatever reason the below configuration works fine:

OD_SCLK:
0:        852Mhz        800mV
1:        979Mhz        825mV
2:       1106Mhz        850mV
3:       1233Mhz        875mV
4:       1360Mhz        900mV
5:       1485Mhz        925mV
6:       1575Mhz       1000mV
7:       1631Mhz       1050mV
OD_MCLK:
0:        167Mhz        800mV
1:        500Mhz        825mV
2:        800Mhz        865mV
3:       1000Mhz       1000mV

Note, I am never hitting P7. Oddly enough, if I leave everything else constant
and change memory state 3 from 3: 1000Mhz 1000mV to 3: 1025Mhz 1000mV, I am
hitting the same issue with memory pstate getting stuck @ 0 (167Mhz).

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