[PATCHv2 13/22] drm/bridge: tc358767: use more reliable seq when finishing LT

[Laurent Pinchart]

Hi Tomi,

Thank you for the patch.

On Tue, Mar 26, 2019 at 12:31:37PM +0200, Tomi Valkeinen wrote:
> At the end of the link training, two steps have to be taken: 1)
> tc358767's LT mode is disabled by a write to DP0_SRCCTRL, and 2) Remove
> LT flag in DPCD 0x102.
> 
> Toshiba's documentation tells to first write the DPCD, then modify
> DP0_SRCCTRL. In my testing this often causes issues, and the link
> disconnects right after those steps.
> 
> If I reverse the steps, it works every time. There's a chance that this
> is DP sink specific, though, but as my testing shows this sequence to be
> much more reliable, let's change it.

As this departs from the documentation I think it deserves a comment in
the code.

> Signed-off-by: Tomi Valkeinen <tomi.valkeinen at ti.com>
> ---
>  drivers/gpu/drm/bridge/tc358767.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c
> index 2a6c0c0d47a6..700e161015af 100644
> --- a/drivers/gpu/drm/bridge/tc358767.c
> +++ b/drivers/gpu/drm/bridge/tc358767.c
> @@ -958,6 +958,9 @@ static int tc_main_link_enable(struct tc_data *tc)
>  	if (ret)
>  		goto err;
>  
> +	/* Clear Training Pattern, set AutoCorrect Mode = 1 */
> +	tc_write(DP0_SRCCTRL, tc_srcctrl(tc) | DP0_SRCCTRL_AUTOCORRECT);
> +
>  	/* Clear DPCD 0x102 */
>  	/* Note: Can Not use DP0_SNKLTCTRL (0x06E4) short cut */
>  	tmp[0] = tc->link.scrambler_dis ? DP_LINK_SCRAMBLING_DISABLE : 0x00;
> @@ -965,9 +968,6 @@ static int tc_main_link_enable(struct tc_data *tc)
>  	if (ret < 0)
>  		goto err_dpcd_write;
>  
> -	/* Clear Training Pattern, set AutoCorrect Mode = 1 */
> -	tc_write(DP0_SRCCTRL, tc_srcctrl(tc) | DP0_SRCCTRL_AUTOCORRECT);
> -
>  	/* Wait */
>  	timeout = 100;
>  	do {

-- 
Regards,

Laurent Pinchart