[PATCH 00/20] drm: Split out the formats API and move it to a common place

Tue Apr 23 19:06:28 UTC 2019

On Tue, Apr 23, 2019 at 7:17 PM Nicolas Dufresne <nicolas at ndufresne.ca> wrote:
>
> Le mardi 23 avril 2019 à 17:09 +0200, Daniel Vetter a écrit :
> > On Tue, Apr 23, 2019 at 4:28 PM Nicolas Dufresne <nicolas at ndufresne.ca> wrote:
> > > Le mardi 23 avril 2019 à 14:33 +0200, Paul Kocialkowski a écrit :
> > > > Hi,
> > > >
> > > > On Tue, 2019-04-23 at 09:30 +0200, Daniel Vetter wrote:
> > > > > On Sun, Apr 21, 2019 at 01:40:45AM +0300, Laurent Pinchart wrote:
> > > > > > Hi Paul,
> > > > > >
> > > > > > On Thu, Apr 18, 2019 at 01:49:54PM +0200, Paul Kocialkowski wrote:
> > > > > > > On Thu, 2019-04-18 at 11:02 +0200, Maxime Ripard wrote:
> > > > > > > > On Thu, Apr 18, 2019 at 09:52:10AM +0200, Daniel Vetter wrote:
> > > > > > > > > And a lot of people pushed for the "fourcc is a standard", when
> > > > > > > > > really it's totally not.
> > > > > > > >
> > > > > > > > Even if it's not a standard, having consistency would be a good thing.
> > > > > > > >
> > > > > > > > And you said yourself that DRM fourcc is now pretty much an authority
> > > > > > > > for the fourcc, so it definitely looks like a standard to me.
> > > > > > >
> > > > > > > I think trying to make the V4L2 and DRM fourccs converge is a lost
> > > > > > > cause, as it has already significantly diverged. Even if we coordinate
> > > > > > > an effort to introduce new formats with the same fourcc on both sides,
> > > > > > > I don't see what good that would be since the formats we have now are
> > > > > > > still plagued by the inconsistency.
> > > > > > >
> > > > > > > I think we always need an explicit translation step from either v4l2 or
> > > > > > > drm to the internal representation and back, without ever assuming that
> > > > > > > formats might be compatible because they share the same fourcc.
> > > > > >
> > > > > > I don't agree. APIs evolve, and while we can't switch from one set of
> > > > > > 4CCs to another in existing APIs, we could in new APIs. Boris is working
> > > > > > on new ioctls to handle formats in V4L2, and while 4CC unification could
> > > > > > be impopular from a userspace developers point of view there, I don't
> > > > > > think we have ruled it out completely. The move to the request API is
> > > > > > also an area where a common set of 4CCs could be used, as it will depart
> > > > > > from the existing V4L2 ioctls. To summarize my opinion, we're not there
> > > > > > yet, but I wouldn't rule it out completely for the future.
> > > > > >
> > > > > > > It looks like so far, V4L2 pixel formats describe a DRM pixel format +
> > > > > > > modifier.
> > > > > >
> > > > > > DRM modifiers are mostly about tiling and compression, and we hardly
> > > > > > support these in V4L2. What are the modifiers you think are hardcoded in
> > > > > > 4CCs in V4L2 ?
> > > > >
> > > > > Hm maybe it was a drm one that didn't come from v4l or anywhere else
> > > > > really, but the NV12MT one is nv12 + some tiling. I think we managed to
> > > > > uapi-bend that one into shape in at least drm.
> > > >
> > > > The one I had in mind is V4L2_PIX_FMT_SUNXI_TILED_NV12 which translates
> > > > to DRM_FORMAT_NV12 + DRM_FORMAT_MOD_ALLWINNER_TILED. Seems to be a
> > > > pretty similar case to the Mediatek one indeed.
> > > >
> > > > In our cause, that's because the video decoding engine produces its
> > > > destination buffers in a specific tiled format, that the display engine
> > > > can take in directly.
> > >
> > > We also have the Samsung tiling (Z pattern) as mentioned here, but also
> > > linear 16x16 tile placement (also from Samsung ?) and I believe Amlogic
> > > CODEC patches is bringing another tiling (unavoidable on older Meson8,
> > > with 64bytes swaps). All these should be expressed as NV12 + mod in DRM
> > > space.
> > >
> > > What is very often not enabled, but affect the performance on mainline
> > > media drivers is the ARM frame buffer compression. I know that RK chips
> > > have support for this, and that you can't achieve the maximum
> > > throughput without that. This one is not documented anywhere, but I
> > > understand that there is multiple variants that HW vendor licence.
> > > Though, in general, each SoC are likely running a single variant, so a
> > > single mod would make sense.
> >
> > We have AFBC modifiers now in drm_fourcc.h, jointly developed by
> > display engineers from ARM and mali gpu reverse engineer people doing
> > the panfrost driver. So should be covered.
> >
> > > So all this to say that V4L2 equally needs supports for these. What I
> > > understood through DRM API is that a buffer allocated for let's say
> > > NV12 + mod, is compatible with linear NV12. That could be used to
> > > simplify some code, but at the same time, a common API that deals with
> > > the padding and alignment of each format + mod independently would do
> > > that same as long as this is not variable depending on which target HW
> > > uses that same format.
> >
> > Not sure why you mean with NV12 + mod is compatible with linear NV12.
> > In general fourcc + modifier != fourcc = linear modifier, size, number
> > of planes, alignment constraints and everything else can be changed by
> > a modifier (and there's examples for all of these, maybe not yet in
> > all cases for NV12, but I think NV12 + AFBC modifiers gives some
> > pretty interesting results). In generally you need to think of the
> > (drm fourcc, modifier) as the pair identified the pixel format, each
> > part individually is fairly meanigless. We have lots of modifiers
> > where the exact tiling mode/layout changes depending upon the fourcc
> > code.
>
> I only meant that the NV12 + mod have the same number of planes, and
> should be large enough to store a linear NV12 equivalent. Not that it
> would render correctly (even though I found it useful to be able to
> render them when I needed to reverse it).

It might be this assumption still holds for nv12, but we've definitely
broken it for other fourcc. You can't rely on this at least being
universally true.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch