[PATCH] drm/amd/display: Allow faking displays as VRR capable.

[Mario Kleiner]

Allow to detect any connected display to be marked as
VRR capable. This is useful for testing the basics of
VRR mode, e.g., scheduling and timestamping, BTR, and
transition logic, on non-VRR capable displays, e.g.,
to perform IGT test-suit kms_vrr test runs.

This fake VRR display mode is enabled by setting the
optional module parameter amdgpu.fakevrrdisplay=1.

It will try to use VRR range info parsed from EDID on
DisplayPort displays which have a compatible EDID,
but not compatible DPCD caps for Adaptive Sync. E.g.,
NVidia G-Sync compatible displays expose a proper EDID,
but not proper DPCD caps.

It will use a hard-coded VRR range of 30 Hz - 144 Hz on
other displays without suitable EDID, e.g., standard
DisplayPort, HDMI, DVI monitors.

Signed-off-by: Mario Kleiner <mario.kleiner.de at gmail.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h           |  1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c       | 11 +++++++
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 30 +++++++++++++++++++
 3 files changed, 42 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 23c3375623d7..351af38e7fd3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -159,6 +159,7 @@ extern uint amdgpu_dc_feature_mask;
 extern struct amdgpu_mgpu_info mgpu_info;
 extern int amdgpu_ras_enable;
 extern uint amdgpu_ras_mask;
+extern int amdgpu_fake_vrr_display;
 
 #ifdef CONFIG_DRM_AMDGPU_SI
 extern int amdgpu_si_support;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 1e2cc9d68a05..3a9fc0fbc76e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -134,6 +134,7 @@ int amdgpu_emu_mode = 0;
 uint amdgpu_smu_memory_pool_size = 0;
 /* FBC (bit 0) disabled by default*/
 uint amdgpu_dc_feature_mask = 0;
+int amdgpu_fake_vrr_display = 0;
 
 struct amdgpu_mgpu_info mgpu_info = {
 	.mutex = __MUTEX_INITIALIZER(mgpu_info.mutex),
@@ -665,6 +666,16 @@ MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (defau
 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))");
 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444);
 
+/**
+ * DOC: fakevrrdisplay (int)
+ * Override detection of VRR displays to mark any display as VRR capable, even
+ * if it is not. Useful for basic testing of VRR without need to attach such a
+ * display, e.g., for igt tests.
+ * Setting 1 enables faking VRR. Default value, 0, does normal detection.
+ */
+module_param_named(fakevrrdisplay, amdgpu_fake_vrr_display, int, 0644);
+MODULE_PARM_DESC(fakevrrdisplay, "Detect any display as VRR capable (0 = off (default), 1 = on)");
+
 static const struct pci_device_id pciidlist[] = {
 #ifdef  CONFIG_DRM_AMDGPU_SI
 	{0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 1854506e3e8f..148ec5bb9fa8 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -6921,6 +6921,15 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
 			edid_check_required = is_dp_capable_without_timing_msa(
 						adev->dm.dc,
 						amdgpu_dm_connector);
+
+			/* Force detection of not-quite adaptive sync capable
+			 * displays as vrr capable if requested by moduleparam.
+			 * Works, e.g., with G-Sync displays.
+			 */
+			if (!edid_check_required && amdgpu_fake_vrr_display) {
+				edid_check_required = true;
+				DRM_INFO("amdgpu.fakevrrdisplay=1 -> Force vrr.\n");
+			}
 		}
 	}
 	if (edid_check_required == true && (edid->version > 1 ||
@@ -6948,6 +6957,12 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
 			amdgpu_dm_connector->max_vfreq = range->max_vfreq;
 			amdgpu_dm_connector->pixel_clock_mhz =
 				range->pixel_clock_mhz * 10;
+
+			DRM_DEBUG("edid vrr %d: %d - %d Hz, clock %d Mhz\n",
+				  i, amdgpu_dm_connector->min_vfreq,
+				  amdgpu_dm_connector->max_vfreq,
+				  amdgpu_dm_connector->pixel_clock_mhz);
+
 			break;
 		}
 
@@ -6958,6 +6973,21 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
 		}
 	}
 
+	/* Fake a vrr display with hard-coded properties if none was
+	 * detected and faking one is requested by module parameter.
+	 */
+	if (!freesync_capable && amdgpu_fake_vrr_display) {
+		freesync_capable = true;
+		amdgpu_dm_connector->min_vfreq = 30;
+		amdgpu_dm_connector->max_vfreq = 144;
+		amdgpu_dm_connector->pixel_clock_mhz = 590;
+
+		DRM_INFO("fake vrr: %d - %d Hz, clock %d Mhz\n",
+			 amdgpu_dm_connector->min_vfreq,
+			 amdgpu_dm_connector->max_vfreq,
+			 amdgpu_dm_connector->pixel_clock_mhz);
+	}
+
 update:
 	if (dm_con_state)
 		dm_con_state->freesync_capable = freesync_capable;
-- 
2.20.1