[PATCH 04/21] drm/dp: Track link capabilities alongside settings

[Andrzej Hajda]

On 05.08.2019 14:23, Thierry Reding wrote:
> From: Thierry Reding <treding at nvidia.com>
>
> Store capabilities in max_* fields and add separate fields for the
> currently selected settings.
>
> Cc: Rob Clark <robdclark at gmail.com>
> Signed-off-by: Thierry Reding <treding at nvidia.com>


For bridge and core part:

Reviewed-by: Andrzej Hajda <a.hajda at samsung.com>

 --
Regards
Andrzej


> ---
>  drivers/gpu/drm/bridge/tc358767.c      | 14 ++++++-------
>  drivers/gpu/drm/drm_dp_helper.c        | 16 ++++++++++-----
>  drivers/gpu/drm/msm/edp/edp_ctrl.c     |  8 ++++----
>  drivers/gpu/drm/rockchip/cdn-dp-core.c |  8 ++++----
>  drivers/gpu/drm/rockchip/cdn-dp-reg.c  | 13 ++++++------
>  drivers/gpu/drm/tegra/dpaux.c          |  8 ++++----
>  drivers/gpu/drm/tegra/sor.c            | 28 +++++++++++++-------------
>  include/drm/drm_dp_helper.h            | 15 +++++++++-----
>  8 files changed, 60 insertions(+), 50 deletions(-)
>
> diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c
> index 42f03a985ac0..a39036e89cf7 100644
> --- a/drivers/gpu/drm/bridge/tc358767.c
> +++ b/drivers/gpu/drm/bridge/tc358767.c
> @@ -437,7 +437,7 @@ static u32 tc_srcctrl(struct tc_data *tc)
>  		reg |= DP0_SRCCTRL_SCRMBLDIS;	/* Scrambler Disabled */
>  	if (tc->link.spread)
>  		reg |= DP0_SRCCTRL_SSCG;	/* Spread Spectrum Enable */
> -	if (tc->link.base.num_lanes == 2)
> +	if (tc->link.base.lanes == 2)
>  		reg |= DP0_SRCCTRL_LANES_2;	/* Two Main Channel Lanes */
>  	if (tc->link.base.rate != 162000)
>  		reg |= DP0_SRCCTRL_BW27;	/* 2.7 Gbps link */
> @@ -674,9 +674,9 @@ static int tc_get_display_props(struct tc_data *tc)
>  		tc->link.base.rate = 270000;
>  	}
>  
> -	if (tc->link.base.num_lanes > 2) {
> +	if (tc->link.base.lanes > 2) {
>  		dev_dbg(tc->dev, "Falling to 2 lanes\n");
> -		tc->link.base.num_lanes = 2;
> +		tc->link.base.lanes = 2;
>  	}
>  
>  	ret = drm_dp_dpcd_readb(&tc->aux, DP_MAX_DOWNSPREAD, &reg);
> @@ -698,7 +698,7 @@ static int tc_get_display_props(struct tc_data *tc)
>  	dev_dbg(tc->dev, "DPCD rev: %d.%d, rate: %s, lanes: %d, framing: %s\n",
>  		tc->link.base.revision >> 4, tc->link.base.revision & 0x0f,
>  		(tc->link.base.rate == 162000) ? "1.62Gbps" : "2.7Gbps",
> -		tc->link.base.num_lanes,
> +		tc->link.base.lanes,
>  		(tc->link.base.capabilities & DP_LINK_CAP_ENHANCED_FRAMING) ?
>  		"enhanced" : "non-enhanced");
>  	dev_dbg(tc->dev, "Downspread: %s, scrambler: %s\n",
> @@ -906,7 +906,7 @@ static int tc_main_link_enable(struct tc_data *tc)
>  
>  	/* Setup Main Link */
>  	dp_phy_ctrl = BGREN | PWR_SW_EN | PHY_A0_EN | PHY_M0_EN;
> -	if (tc->link.base.num_lanes == 2)
> +	if (tc->link.base.lanes == 2)
>  		dp_phy_ctrl |= PHY_2LANE;
>  
>  	ret = regmap_write(tc->regmap, DP_PHY_CTRL, dp_phy_ctrl);
> @@ -1094,7 +1094,7 @@ static int tc_main_link_enable(struct tc_data *tc)
>  		ret = -ENODEV;
>  	}
>  
> -	if (tc->link.base.num_lanes == 2) {
> +	if (tc->link.base.lanes == 2) {
>  		value = (tmp[0] >> 4) & DP_CHANNEL_EQ_BITS;
>  
>  		if (value != DP_CHANNEL_EQ_BITS) {
> @@ -1291,7 +1291,7 @@ static enum drm_mode_status tc_mode_valid(struct drm_bridge *bridge,
>  		return MODE_CLOCK_HIGH;
>  
>  	req = mode->clock * bits_per_pixel / 8;
> -	avail = tc->link.base.num_lanes * tc->link.base.rate;
> +	avail = tc->link.base.lanes * tc->link.base.rate;
>  
>  	if (req > avail)
>  		return MODE_BAD;
> diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
> index f5af71ec1b7d..365de63a02fb 100644
> --- a/drivers/gpu/drm/drm_dp_helper.c
> +++ b/drivers/gpu/drm/drm_dp_helper.c
> @@ -342,9 +342,12 @@ static void drm_dp_link_reset(struct drm_dp_link *link)
>  		return;
>  
>  	link->revision = 0;
> -	link->rate = 0;
> -	link->num_lanes = 0;
> +	link->max_rate = 0;
> +	link->max_lanes = 0;
>  	link->capabilities = 0;
> +
> +	link->rate = 0;
> +	link->lanes = 0;
>  }
>  
>  /**
> @@ -370,12 +373,15 @@ int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link)
>  		return err;
>  
>  	link->revision = values[0];
> -	link->rate = drm_dp_bw_code_to_link_rate(values[1]);
> -	link->num_lanes = values[2] & DP_MAX_LANE_COUNT_MASK;
> +	link->max_rate = drm_dp_bw_code_to_link_rate(values[1]);
> +	link->max_lanes = values[2] & DP_MAX_LANE_COUNT_MASK;
>  
>  	if (values[2] & DP_ENHANCED_FRAME_CAP)
>  		link->capabilities |= DP_LINK_CAP_ENHANCED_FRAMING;
>  
> +	link->rate = link->max_rate;
> +	link->lanes = link->max_lanes;
> +
>  	return 0;
>  }
>  EXPORT_SYMBOL(drm_dp_link_probe);
> @@ -462,7 +468,7 @@ int drm_dp_link_configure(struct drm_dp_aux *aux, struct drm_dp_link *link)
>  	int err;
>  
>  	values[0] = drm_dp_link_rate_to_bw_code(link->rate);
> -	values[1] = link->num_lanes;
> +	values[1] = link->lanes;
>  
>  	if (link->capabilities & DP_LINK_CAP_ENHANCED_FRAMING)
>  		values[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;