[PATCH v3 6/8] drm/panfrost: Add cache/TLB flush before switching address space

[Robin Murphy]

On 26/08/2019 23:33, Rob Herring wrote:
> It's not entirely clear if this is required, but add a flush of GPU caches
> and TLBs before we change an address space to new page tables.

This might work out to be partially redundant with some of the revamped 
flushing in #7, but unless it proves to be a performance bottleneck, 
having both does make things seem more robust and easier to reason about.

Reviewed-by: Robin Murphy <robin.murphy at arm.com>

> Fixes: 7282f7645d06 ("drm/panfrost: Implement per FD address spaces")
> Cc: Tomeu Vizoso <tomeu.vizoso at collabora.com>
> Cc: Steven Price <steven.price at arm.com>
> Cc: Alyssa Rosenzweig <alyssa.rosenzweig at collabora.com>
> Cc: David Airlie <airlied at linux.ie>
> Cc: Daniel Vetter <daniel at ffwll.ch>
> Signed-off-by: Rob Herring <robh at kernel.org>
> ---
>   drivers/gpu/drm/panfrost/panfrost_mmu.c | 2 ++
>   1 file changed, 2 insertions(+)
> v3:
>   - New patch
> 
> diff --git a/drivers/gpu/drm/panfrost/panfrost_mmu.c b/drivers/gpu/drm/panfrost/panfrost_mmu.c
> index 3407b00d0a3a..d1ebde3327fe 100644
> --- a/drivers/gpu/drm/panfrost/panfrost_mmu.c
> +++ b/drivers/gpu/drm/panfrost/panfrost_mmu.c
> @@ -115,6 +115,8 @@ static void panfrost_mmu_enable(struct panfrost_device *pfdev, struct panfrost_m
>   	u64 transtab = cfg->arm_mali_lpae_cfg.transtab;
>   	u64 memattr = cfg->arm_mali_lpae_cfg.memattr;
> 
> +	mmu_hw_do_operation_locked(pfdev, as_nr, 0, ~0UL, AS_COMMAND_FLUSH_MEM);
> +
>   	mmu_write(pfdev, AS_TRANSTAB_LO(as_nr), transtab & 0xffffffffUL);
>   	mmu_write(pfdev, AS_TRANSTAB_HI(as_nr), transtab >> 32);
> 
> --
> 2.20.1
>