[radeon-alex:drm-next-5.1-wip 197/225] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:5173:4: note: in expansion of macro 'amdgpu_dm_crtc_set_crc_source'
kbuild test robot
lkp at intel.com
Sat Feb 2 05:45:20 UTC 2019
tree: git://people.freedesktop.org/~agd5f/linux.git drm-next-5.1-wip
head: f9028b9278422fdf186f1b88662e28ed24e13df8
commit: 43a6a02eb3558d1f3a0618f9bf02328662fb06e3 [197/225] drm/amd/display: Re-enable CRC capture following modeset
config: x86_64-randconfig-s2-02021031 (attached as .config)
compiler: gcc-6 (Debian 6.5.0-2) 6.5.0 20181026
reproduce:
git checkout 43a6a02eb3558d1f3a0618f9bf02328662fb06e3
# save the attached .config to linux build tree
make ARCH=x86_64
All error/warnings (new ones prefixed by >>):
In file included from include/uapi/linux/posix_types.h:5:0,
from include/uapi/linux/types.h:14,
from include/linux/types.h:6,
from include/uapi/linux/byteorder/little_endian.h:12,
from include/linux/byteorder/little_endian.h:5,
from arch/x86/include/uapi/asm/byteorder.h:5,
from drivers/gpu/drm/amd/amdgpu/../display/dc/os_types.h:29,
from drivers/gpu/drm/amd/amdgpu/../display/dc/dm_services_types.h:29,
from drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:29:
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c: In function 'amdgpu_dm_atomic_commit_tail':
>> include/linux/stddef.h:8:14: error: called object is not a function or function pointer
#define NULL ((void *)0)
^
>> drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.h:340:39: note: in expansion of macro 'NULL'
#define amdgpu_dm_crtc_set_crc_source NULL
^~~~
>> drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:5173:4: note: in expansion of macro 'amdgpu_dm_crtc_set_crc_source'
amdgpu_dm_crtc_set_crc_source(crtc, "auto");
^
vim +/amdgpu_dm_crtc_set_crc_source +5173 drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c
4949
4950 /**
4951 * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation.
4952 * @state: The atomic state to commit
4953 *
4954 * This will tell DC to commit the constructed DC state from atomic_check,
4955 * programming the hardware. Any failures here implies a hardware failure, since
4956 * atomic check should have filtered anything non-kosher.
4957 */
4958 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
4959 {
4960 struct drm_device *dev = state->dev;
4961 struct amdgpu_device *adev = dev->dev_private;
4962 struct amdgpu_display_manager *dm = &adev->dm;
4963 struct dm_atomic_state *dm_state;
4964 struct dc_state *dc_state = NULL, *dc_state_temp = NULL;
4965 uint32_t i, j;
4966 struct drm_crtc *crtc;
4967 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
4968 unsigned long flags;
4969 bool wait_for_vblank = true;
4970 struct drm_connector *connector;
4971 struct drm_connector_state *old_con_state, *new_con_state;
4972 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
4973 int crtc_disable_count = 0;
4974
4975 drm_atomic_helper_update_legacy_modeset_state(dev, state);
4976
4977 dm_state = dm_atomic_get_new_state(state);
4978 if (dm_state && dm_state->context) {
4979 dc_state = dm_state->context;
4980 } else {
4981 /* No state changes, retain current state. */
4982 dc_state_temp = dc_create_state();
4983 ASSERT(dc_state_temp);
4984 dc_state = dc_state_temp;
4985 dc_resource_state_copy_construct_current(dm->dc, dc_state);
4986 }
4987
4988 /* update changed items */
4989 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
4990 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
4991
4992 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
4993 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
4994
4995 DRM_DEBUG_DRIVER(
4996 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
4997 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
4998 "connectors_changed:%d\n",
4999 acrtc->crtc_id,
5000 new_crtc_state->enable,
5001 new_crtc_state->active,
5002 new_crtc_state->planes_changed,
5003 new_crtc_state->mode_changed,
5004 new_crtc_state->active_changed,
5005 new_crtc_state->connectors_changed);
5006
5007 /* Copy all transient state flags into dc state */
5008 if (dm_new_crtc_state->stream) {
5009 amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base,
5010 dm_new_crtc_state->stream);
5011 }
5012
5013 /* handles headless hotplug case, updating new_state and
5014 * aconnector as needed
5015 */
5016
5017 if (modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) {
5018
5019 DRM_DEBUG_DRIVER("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc);
5020
5021 if (!dm_new_crtc_state->stream) {
5022 /*
5023 * this could happen because of issues with
5024 * userspace notifications delivery.
5025 * In this case userspace tries to set mode on
5026 * display which is disconnected in fact.
5027 * dc_sink is NULL in this case on aconnector.
5028 * We expect reset mode will come soon.
5029 *
5030 * This can also happen when unplug is done
5031 * during resume sequence ended
5032 *
5033 * In this case, we want to pretend we still
5034 * have a sink to keep the pipe running so that
5035 * hw state is consistent with the sw state
5036 */
5037 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
5038 __func__, acrtc->base.base.id);
5039 continue;
5040 }
5041
5042 if (dm_old_crtc_state->stream)
5043 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
5044
5045 pm_runtime_get_noresume(dev->dev);
5046
5047 acrtc->enabled = true;
5048 acrtc->hw_mode = new_crtc_state->mode;
5049 crtc->hwmode = new_crtc_state->mode;
5050 } else if (modereset_required(new_crtc_state)) {
5051 DRM_DEBUG_DRIVER("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
5052
5053 /* i.e. reset mode */
5054 if (dm_old_crtc_state->stream)
5055 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
5056 }
5057 } /* for_each_crtc_in_state() */
5058
5059 if (dc_state) {
5060 dm_enable_per_frame_crtc_master_sync(dc_state);
5061 mutex_lock(&dm->dc_lock);
5062 WARN_ON(!dc_commit_state(dm->dc, dc_state));
5063 mutex_unlock(&dm->dc_lock);
5064 }
5065
5066 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
5067 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
5068
5069 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
5070
5071 if (dm_new_crtc_state->stream != NULL) {
5072 const struct dc_stream_status *status =
5073 dc_stream_get_status(dm_new_crtc_state->stream);
5074
5075 if (!status)
5076 status = dc_stream_get_status_from_state(dc_state,
5077 dm_new_crtc_state->stream);
5078
5079 if (!status)
5080 DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc);
5081 else
5082 acrtc->otg_inst = status->primary_otg_inst;
5083 }
5084 }
5085
5086 /* Handle connector state changes */
5087 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
5088 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
5089 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
5090 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
5091 struct dc_surface_update dummy_updates[MAX_SURFACES] = { 0 };
5092 struct dc_stream_update stream_update = { 0 };
5093 struct dc_stream_status *status = NULL;
5094
5095 if (acrtc) {
5096 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
5097 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
5098 }
5099
5100 /* Skip any modesets/resets */
5101 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state))
5102 continue;
5103
5104 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
5105 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
5106
5107 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state) &&
5108 (dm_new_crtc_state->abm_level == dm_old_crtc_state->abm_level))
5109 continue;
5110
5111 if (is_scaling_state_different(dm_new_con_state, dm_old_con_state)) {
5112 update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode,
5113 dm_new_con_state, (struct dc_stream_state *)dm_new_crtc_state->stream);
5114
5115 stream_update.src = dm_new_crtc_state->stream->src;
5116 stream_update.dst = dm_new_crtc_state->stream->dst;
5117 }
5118
5119 if (dm_new_crtc_state->abm_level != dm_old_crtc_state->abm_level) {
5120 dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level;
5121
5122 stream_update.abm_level = &dm_new_crtc_state->abm_level;
5123 }
5124
5125 status = dc_stream_get_status(dm_new_crtc_state->stream);
5126 WARN_ON(!status);
5127 WARN_ON(!status->plane_count);
5128
5129 /*
5130 * TODO: DC refuses to perform stream updates without a dc_surface_update.
5131 * Here we create an empty update on each plane.
5132 * To fix this, DC should permit updating only stream properties.
5133 */
5134 for (j = 0; j < status->plane_count; j++)
5135 dummy_updates[j].surface = status->plane_states[0];
5136
5137
5138 mutex_lock(&dm->dc_lock);
5139 dc_commit_updates_for_stream(dm->dc,
5140 dummy_updates,
5141 status->plane_count,
5142 dm_new_crtc_state->stream,
5143 &stream_update,
5144 dc_state);
5145 mutex_unlock(&dm->dc_lock);
5146 }
5147
5148 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
5149 new_crtc_state, i) {
5150 /*
5151 * loop to enable interrupts on newly arrived crtc
5152 */
5153 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
5154 bool modeset_needed;
5155
5156 if (old_crtc_state->active && !new_crtc_state->active)
5157 crtc_disable_count++;
5158
5159 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
5160 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
5161 modeset_needed = modeset_required(
5162 new_crtc_state,
5163 dm_new_crtc_state->stream,
5164 dm_old_crtc_state->stream);
5165
5166 if (dm_new_crtc_state->stream == NULL || !modeset_needed)
5167 continue;
5168
5169 manage_dm_interrupts(adev, acrtc, true);
5170
5171 /* The stream has changed so CRC capture needs to re-enabled. */
5172 if (dm_new_crtc_state->crc_enabled)
> 5173 amdgpu_dm_crtc_set_crc_source(crtc, "auto");
5174 }
5175
5176 /* update planes when needed per crtc*/
5177 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) {
5178 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
5179
5180 if (dm_new_crtc_state->stream)
5181 amdgpu_dm_commit_planes(state, dc_state, dev,
5182 dm, crtc, &wait_for_vblank);
5183 }
5184
5185
5186 /*
5187 * send vblank event on all events not handled in flip and
5188 * mark consumed event for drm_atomic_helper_commit_hw_done
5189 */
5190 spin_lock_irqsave(&adev->ddev->event_lock, flags);
5191 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
5192
5193 if (new_crtc_state->event)
5194 drm_send_event_locked(dev, &new_crtc_state->event->base);
5195
5196 new_crtc_state->event = NULL;
5197 }
5198 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
5199
5200 /* Signal HW programming completion */
5201 drm_atomic_helper_commit_hw_done(state);
5202
5203 if (wait_for_vblank)
5204 drm_atomic_helper_wait_for_flip_done(dev, state);
5205
5206 drm_atomic_helper_cleanup_planes(dev, state);
5207
5208 /*
5209 * Finally, drop a runtime PM reference for each newly disabled CRTC,
5210 * so we can put the GPU into runtime suspend if we're not driving any
5211 * displays anymore
5212 */
5213 for (i = 0; i < crtc_disable_count; i++)
5214 pm_runtime_put_autosuspend(dev->dev);
5215 pm_runtime_mark_last_busy(dev->dev);
5216
5217 if (dc_state_temp)
5218 dc_release_state(dc_state_temp);
5219 }
5220
---
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