[PATCH 2/2] drm/arm/hdlcd: Allow a bit of clock tolerance

[Liviu Dudau]

On Fri, May 17, 2019 at 05:37:22PM +0100, Robin Murphy wrote:
> On the Arm Juno platform, the HDLCD pixel clock is constrained to 250KHz
> resolution in order to avoid the tiny System Control Processor spending
> aeons trying to calculate exact PLL coefficients. This means that modes
> like my oddball 1600x1200 with 130.89MHz clock get rejected since the
> rate cannot be matched exactly. In practice, though, this mode works
> quite happily with the clock at 131MHz, so let's relax the check to
> allow a little bit of slop.
> 
> Signed-off-by: Robin Murphy <robin.murphy at arm.com>

Acked-by: Liviu Dudau <liviu.dudau at arm.com>

I've pull the two patches into my malidp-fixes branch and I will send a pull
request today.

Best regards,
Liviu

> ---
>  drivers/gpu/drm/arm/hdlcd_crtc.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/arm/hdlcd_crtc.c b/drivers/gpu/drm/arm/hdlcd_crtc.c
> index ecac6fe0b213..a3efa28436ea 100644
> --- a/drivers/gpu/drm/arm/hdlcd_crtc.c
> +++ b/drivers/gpu/drm/arm/hdlcd_crtc.c
> @@ -193,7 +193,8 @@ static enum drm_mode_status hdlcd_crtc_mode_valid(struct drm_crtc *crtc,
>  	long rate, clk_rate = mode->clock * 1000;
>  
>  	rate = clk_round_rate(hdlcd->clk, clk_rate);
> -	if (rate != clk_rate) {
> +	/* 0.1% seems a close enough tolerance for the TDA19988 on Juno */
> +	if (abs(rate - clk_rate) * 1000 > clk_rate) {
>  		/* clock required by mode not supported by hardware */
>  		return MODE_NOCLOCK;
>  	}
> -- 
> 2.21.0.dirty
> 
> _______________________________________________
> dri-devel mailing list
> dri-devel at lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel

-- 
====================
| I would like to |
| fix the world,  |
| but they're not |
| giving me the   |
 \ source code!  /
  ---------------
    ¯\_(ツ)_/¯