[PATCH v2] drm/fourcc: add ARM GPU tile format

[Qiang Yu]

Alyssa did a very good description of our needs. Since I can't open the
cgit mesa link and give you a clear view of this format:
https://gitlab.freedesktop.org/mesa/mesa/blob/master/src/gallium/drivers/panfrost/pan_swizzle.c
https://gitlab.freedesktop.org/lima/mesa/blob/lima-18.3/src/gallium/drivers/lima/lima_tiling.c#L29

Thanks,
Qiang

On Tue, Mar 12, 2019 at 12:39 AM Alyssa Rosenzweig <alyssa at rosenzweig.io> wrote:
>
> > You might want to re-use the exisiting modifier
> > AFBC_FORMAT_MOD_BLOCK_SIZE_16x16.
> >
> > I would suggest you to have a look at the exisiting AFBC modifiers
> > (denoted by AFBC_FORMAT_MOD_XXX ) and let us know if there is
> > something you cannot reuse.
>
> So, the "tiled" format in question (that Qiang needs to import/export
> BOs in) is *uncompressed* but tiled with an Arm-internal format (for the
> GPUs).  Here's a software implementation for encoding this format:
> https://cgit.freedesktop.org/mesa/mesa/tree/src/gallium/drivers/panfrost/pan_swizzle.c
>
> For Midgard/Bifrost, we use this tiling internally for uploading bitmap
> textures, but we only render to AFBC (or linear). So for Panfrost, we'll
> always be importing/exporting AFBC buffers, never uncompressed tiled.
> But Utgard does not seem to support AFBC (?), so Qiang needs the
> uncompressed tiled for the same purpose Panfrost uses AFBC.
>
> Is it possible that this is the same tiling used internally by
> AFBC_FORMAT_MOD_BLOCK_SIZE_16x16, only without any compression? AFBC is
> blackbox for us, so this isn't something we can figure out ourselves,
> but that influences whether it's appropriate to reuse the modifier. If
> this is the same tiling scheme, perhaps that's the answer. If it's not
> (I don't know how AFBC tiling works), we probably do need a separate
> modifier to avoid confusion.
>
> Thanks,
>
> Alyssa
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